ISPPAC-POWR1014A LATTICE [Lattice Semiconductor], ISPPAC-POWR1014A Datasheet - Page 24

• Manufacturer Part Number: ISPPAC-POWR1014A
• Description: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
The ispPAC-POWR1014A’s I
write transaction (Figure 15) consists of the following operations:
To start the transaction, the master device holds the SCL line high while pulling SDA low. Address and data bits are
then transferred on each successive SCL pulse, in three consecutive byte frames of 9 SCL pulses. Address and
data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave
device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format.
The first frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. The second frame
contains the register address to which data will be written, and the final frame contains the actual data to be writ-
ten. Note that the SDA signal is only allowed to change when the SCL is low, as raising SDA when SCL is high sig-
nals the end of the transaction.
Figure 15. I
Reading a data byte from the ispPAC-POWR1014A requires two separate bus transactions (Figure 16). The first
transaction writes the register address from which a data byte is to be read. Note that since no data is being written
to the device, the transaction is concluded after the second byte frame. The second transaction performs the actual
read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the ispPAC-
POWR1014A asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the
second frame is asserted by the master device and not the ispPAC-POWR1014A.
Figure 16. I
The ispPAC-POWR1014A provides 17 registers that can be accessed through its I
provide the user with the ability to monitor and control the device’s inputs and outputs, and transfer data to and
from the device. Table 7 provides a summary of these registers.
1. Start the bus transaction
2. Transmit the device address (7 bits) along with a low write bit
3. Transmit the address of the register to be written to (8 bits)
4. Transmit the data to be written (8 bits)
5. Stop the bus transaction
SDA
STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION
STEP 2: READ DATA FROM THAT REGISTER
SCL
SDA
SDA
2
2
SCL
SCL
START
C Write Operation
C Read Operation
START
START
A6
1
A5
2
A4
DEVICE ADDRESS (7 BITS)
3
A6
A6
1
1
A3
4
A5
A5
2
2
2
C/SMBus interface allows data to be both written to and read from the device. A data
A2
5
A4
A4
A1
DEVICE ADDRESS (7 BITS)
DEVICE ADDRESS (7 BITS)
6
3
3
A0
7
A3
A3
4
4
R/W
8
A2
A2
5
5
ACK
9
A1
A1
6
6
R7
1
A0
A0
7
7
R6
2
R/W
R/W
REGISTER ADDRESS (8 BITS)
R5
3
8
8
R4
4
ACK
ACK
24
9
9
R3
5
R2
6
R7
D7
1
1
R1
7
R6
R0
D6
8
2
2
ACK
REGISTER ADDRESS (8 BITS)
9
R5
D5
3
3
ispPAC-POWR1014/A Data Sheet
READ DATA (8 BITS)
R4
D7
D4
1
4
4
D6
2
R3
D3
5
5
D5
3
WRITE DATA (8 BITS)
R2
D2
6
6
Note: Shaded Bits Asserted by Slave
D4
4
2
C interface. These registers
R1
D3
D1
5
7
7
Note: Shaded Bits Asserted by Slave
D2
6
R0
D0
8
8
OPTIONAL
D1
7
ACK
ACK
9
9
D0
8
ACK
9
STOP
STOP
STOP