ISPPAC-POWR1014A LATTICE [Lattice Semiconductor], ISPPAC-POWR1014A Datasheet - Page 40

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ISPPAC-POWR1014A

Manufacturer Part Number
ISPPAC-POWR1014A
Description
In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet

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ispPAC-POWR1014/A Data Sheet
PROGRAM_DONE_BIT – This instruction sets the 'Done' bit, which enables the ispPAC-POWR1014/A sequence
to start.
RESET – This instruction resets the PLD sequence and output macrocells.
IN1_RESET_JTAG_BIT – This instruction clears the JTAG Register logic input 'IN1.' The PLD input has to be con-
figured to take input from the JTAG Register in order for this command to have effect on the sequence.
IN1_SET_JTAG_BIT – This instruction sets the JTAG Register logic input 'IN1.' The PLD input has to be configured
to take input from the JTAG Register in order for this command to have effect on the sequence.
PLD_VERIFY_INCR – This instruction reads out the PLD data register for the current address and increments the
address register for the next read.
Notes:
In all of the descriptions above, OUTPUTS_HIGHZ refers both to the instruction and the state of the digital output
pins, in which the open-drains are tri-stated and the FET drivers are pulled low.
2
Before any of the above programming instructions are executed, the respective E
CMOS bits need to be erased
using the corresponding erase instruction.
40

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