ISPPAC30-01SI LATTICE [Lattice Semiconductor], ISPPAC30-01SI Datasheet - Page 5

• Manufacturer Part Number: ISPPAC30-01SI
• Description: In-System Programmable Analog Circuit
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Pin Descriptions
15, 16, 17, 18,
25, 26, 27, 28
5, 10, 19, 24
21, 22
PDIP
20
13
12
11
14
23
6
4
9
8
7
3
2
1
Pins
13, 14, 15, 16,
21, 22, 23, 24
18, 19
SOIC
17
11
10
12
20
—
5
4
9
8
7
6
3
2
1
VREFOUT
Symbol
MSEL1
MSEL2
ENSPI
SCOM
GND
OUT
TMS
TDO
TCK
CAL
TDI
NC
CS
PD
VS
IN
Voltage Reference Output
Inputs 1, 2, 3, 4 (+ or -)
Multiplexer 1 Control
Multiplexer 2 Control
Enable SPI Mode
Test Mode Select
Outputs 1 and 2
Signal Common
Supply Voltage
Auto-Calibrate
Test Data Out
Plus or Minus
No Connects
Power Down
Test Data In
Chip Select
Test Clock
Ground
Name
5
Differential input pins, with two pins per input
(e.g., IN2+ and IN2-). Each are components of
V
Multiplexer logic input pin. Selects either of two
analog channels to IA1 (instrument amplifier).
Programmable pull-up, pull-down (default), or
none.
Multiplexer logic input pin. Selects either of two
analog channels to IA4 (instrument amplifier).
Programmable pull-up, pull-down (default), or
none.
Single-ended output pins. Internal feedback to
inputs accommodated.
Internal voltage reference output pin (+2.5V
nominal). Must be bypassed to GND with a 1µF
capacitor.
Enable SPI logic input pin. When high, causes
serial port to run in SPI mode. Programmable
pull-up or pull-down (default).
Serial interface logic mode select pin (input).
JTAG interface mode only. Internal pull-up.
Serial interface logic pin (output) for both JTAG
and SPI operation modes. Programmable slew
rate, high or low (default).
Serial interface logic pin (input) for both JTAG
and SPI modes. Internal pull-up.
Serial interface logic clock pin (input) for both
JTAG and SPI modes. Programmable pull-up,
pull-down (default), or none.
Chip select logic input pin. SPI data transfer
enabled by this input. Internal pull-up.
Digital pin (input). Commands an auto-calibration
sequence on a rising edge. Internal pull-down.
Power down enable logic pin (input). Shuts down
all power to device. Programmable pull-up
(default), pull-down or none.
Analog supply pin (5V nominal). Should be
bypassed to GND with 1µF and .01µF capaci-
tors.
Ground pin. Should normally be connected to
the analog ground plane.
Analog signal common pin (sense). Always con-
nected to GND. Auto-calibration accuracy is
determined with respect to this pin.
No internal connections are made to these pins
in the PDIP package.
ispPAC30 Preliminary Data Sheet
IN
, where differential V
Description
IN
= V
IN+
- V
IN-
.