AGL015V2-CS144 ACTEL [Actel Corporation], AGL015V2-CS144 Datasheet - Page 17
AGL015V2-CS144
Manufacturer Part Number
AGL015V2-CS144
Description
IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.AGL015V2-CS144.pdf
(212 pages)
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Table 2-4 •
V
2.7 V or less
3 V
3.3 V
3.6 V
Notes:
1. Based on reliability requirements at junction temperature at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two
3. This table does not provide PCI overshoot/undershoot limits.
CCI
cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOO device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In
addition, the I/O will be in a known state through the power-up sequence. The basic principle is
shown in
There are five regions to consider during power-up.
IGLOO I/Os are activated only if ALL of the following three conditions are met:
V
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V
Ramping down (V5 Devices): 0.5 V < trip_point_down < 1.1 V
Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V
V
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V
Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V
V
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note
the following:
Overshoot and Undershoot Limits
CC
CCI
CC
1. V
2. V
3. Chip is in the operating mode.
•
•
Trip Point:
and V
Trip Point:
Figure 2-2 on page
During programming, I/Os become tristated and weakly pulled up to V
JTAG supply, PLL power supplies, and charge pump V
behavior.
CC
CCI
Figure 2-1 on page 2-4
CCI
and V
> V
ramp-up trip points are about 100 mV higher than ramp-down trip points. This
CC
– 0.75 V (typical)
CCI
Average V
as a Percentage of Clock Cycle
are above the minimum specified trip points
Undershoot Duration
2-5).
CCI
and
–GND Overshoot or
10%
10%
10%
10%
1
5%
5%
5%
5%
A dv a n c e v 0. 5
Figure 2-2 on page
2
2-5.
PUMP
IGLOO DC and Switching Characteristics
supply have no influence on I/O
(Figure 2-1 on page 2-4
Maximum Overshoot/
Undershoot
CCI
1.49 V
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
1.4 V
1.1 V
.
2
and
2 - 3
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