OX16C950 OXFORD [Oxford Semiconductor], OX16C950 Datasheet - Page 17

• Manufacturer Part Number: OX16C950
• Description: High Performance UART with 128 byte FIFOs
• Manufacturer: OXFORD [Oxford Semiconductor]

Note 10: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the indexed control registers
Data Sheet Revision 1.2
OXFORD SEMICONDUCTOR LTD.
Indexed Control Register Set
Register
Name
MDM
PIDX
NMR
GDS
DMS
ACR
CPR
TCR
CKS
FCH
REV
CSR
RFC
CKA
RTL
FCL
TTL
ID1
ID2
ID3
via ICR. Offset values not listed in the table are reserved for future use and must not be used.
To read or write to any of the Indexed Control Registers use the following procedure.
Writing to ICR registers:
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).
Write the desired offset to SPR (address 111
Offset
SPR
0x0C
0x0D
0X0F
0X10
0x00
0x01
0x03
0x05
0x0A
0x0B
0x0E
0x11
0x13
0x02
0x04
0x06
0x07
0x08
0x09
0x12
10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
Unused
Unused
Unused
Unused
inactive
Enable
FCR[7]
Status
TxRdy
Bit 7
Addit-
Mode
Force
Tx 1x
ional
Unused
Table 7: Indexed Control Register Set
Unused
inactive
Enable
Tx CLK
FCR[6]
RxRdy
Select
Bit 6
Force
Read
2
ICR
).
5 Bit “integer” part of
Unused
Unused
clock prescaler
reset the UART (Except the CKS and CKA registers)
SChar 4
BDOUT
Trigger
on DTR
Enable
FCR[5]
Bit 5
9
Level
950
th
Automatic Flow Control Lower Trigger Level (0-127)
Automatic Flow Control Higher Trigger level (1-127)
Bit
Writing 0x00 to this register will
Hardwired revision byte (0x03)
Hardwired Port Index ( 0x00 )
Transmitter Interrupt Trigger Level (0-127)
Hardwired ID byte 1 (0xC9)
Receiver Interrupt Trigger Level (1-127)
Hardwired ID byte 1 (0x16)
Hardwired ID byte 1 (0x50)
on txrdy
Schar 3
Unused
DTR 1x
Tx CLK
FCR[4]
sys-clk
Output
Bit 4
DTR definition and
9
th
Bit
Unused
control
CLKSEL
SChar 2
Wakeup
∆ DCD
disable
FCR[3]
sys-clk
pin for
Bit 3
9
Rx 1x
Mode
Use
th
Bit
SChar 1
RI edge
Trailing
Control
Enable
BDOUT
disable
FCR[2]
Disable
Bit 2
9
signal
4 Bit N-times clock
Invert
DSR
Flow
selection bits [3:0]
Auto
DTR
th
Bit
3 Bit “fractional” part of
clock prescaler
OX16C950 rev B
9
Wakeup
Disable
tx clock
disable
internal
th
∆ DSR
FCR[1]
TxRdy
Bit 1
status
Invert
-bit Int.
( R )
En.
Tx
Clock Sel[1:0]
Receiver
Wakeup
rx clock
Disable
disable
internal
Enable
FCR[0]
∆ CTS
RxRdy
Status
Bit 0
status
Good
Invert
Data
Page 17
9 Bit
( R )
Rx