OX16C950 OXFORD [Oxford Semiconductor], OX16C950 Datasheet - Page 8
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OX16C950
Manufacturer Part Number
OX16C950
Description
High Performance UART with 128 byte FIFOs
Manufacturer
OXFORD [Oxford Semiconductor]
Datasheet
1.OX16C950.pdf
(49 pages)
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4
Data Sheet Revision 1.2
OXFORD SEMICONDUCTOR LTD.
PLCC
Clock
18
19
23
Processor Interface
39
14, 15
16
29 -31
28
9 - 2
26
20
21
24
25
P
IN
D
ESCRIPTIONS
TQFP
14
15
21
35
9,
10
11
26 – 28
24
4 – 2,
47 – 43
22
16
17
19
20
Dir
I
O
IU
I
I
I
I
I
I/O
O
I
I
I
I
1
Name
XTLI
XTLO
CLKSEL
RESET
CS0,CS1
CS2#
A[2:0]
ADS#
DB[7:0]
DDIS
IOW#
IOW
IOR#
IOR
Address lines to select channel registers.
Description
Crystal oscillator input or external clock pin.
Maximum frequency 60 MHz @ 5V, 50 MHz @ 3.3V
Crystal oscillator output. Not used when an alternative TTL level clock is
applied to XTLI and can be left unconnected.
The state of this pin on power up configures the internal clock prescaler. This
pin has an internal pull-up. When CLKSEL pin is high the pre-scalar is
bypassed. Connect this pin to GND to enable the internal clock prescaler
(see section 14.2). The complement of this pin is loaded in MCR[7] after a
hardware reset.
This pin can also be used as an alternative external clock pin under software
control (replacing XTLI and thus reducing noise/power due to XTLO) for
embedded applications
Active-high hardware reset. Hardware reset is described in section 7.1. This
pin must be tied inactive when not in use.
Active-high chip select. All chip select pins must be active for the device to
be selected.
Active-low chip select.
Active-low address strobe. When ADS# signal is low, the address (A[2:0])
and chip select signal (CS0, CS1, CS2#) drive the internal logic, otherwise
they are latched at the level they were when low-to-high transition of ADS#
signal occurred. This pin is used when address and chip selects are not
stable during read or write cycles. If this functionality is not required, this pin
can be permanently tied to GND.
Eight-bit 3-state data bus.
Drive Disable. This pin goes active (high) when CPU is not reading from
OX16C950. This signal can be used to disable an external transceiver.
Active-low write strobe. When IOW# is used to write the chip, IOW should be
tied low (inactive).
Active-high write strobe. When IOW is used to write the chip, IOW# should be
tied high (inactive).
Active-low read strobe. When IOR# is used to read from the chip, IOR should
be tied low (inactive).
Active-high read strobe. When IOR is used to read from the chip, IOR#
should be tied high (inactive).
OX16C950 rev B
Page 8