OX16C950 OXFORD [Oxford Semiconductor], OX16C950 Datasheet - Page 21

• Manufacturer Part Number: OX16C950
• Description: High Performance UART with 128 byte FIFOs
• Manufacturer: OXFORD [Oxford Semiconductor]

650 mode:
In 650 mode the transmitter interrupt trigger levels are set
to the following values:
These levels only apply when in Enhanced mode and in
DMA mode 1 (FCR[3] = 1), otherwise the trigger level is set
to 1. A transmitter empty interrupt will be generated (if
enabled) if the TFL falls below the trigger level.
750 Mode:
In 750 compatible non-Enhanced (EFR[4]=0) mode,
transmitter trigger level is set to 1, FCR[4] is unused and
FCR[5] defines the FIFO depth as follows:
FCR[5]=0 Transmitter and receiver FIFO size is 16 bytes.
FCR[5]=1 Transmitter and receiver FIFO size is 128 bytes.
In non-Enhanced mode and when FIFOSEL pin is low,
FCR[5] is only writable when LCR[7] is set. Note that in
Enhanced mode, the FIFO size is also increased to 128
bytes when FCR[0] is set.
950 mode:
Setting ACR[5]=1 enables arbitrary transmitter trigger level
setting using the TTL register (see section 15.4), hence
FCR[5:4] are ignored.
FCR[7:6]: RHR trigger level
In 550, extended 550, 650 and 750 modes, the receiver
FIFO trigger levels are defined using FCR[7:6]. The
interrupt trigger level and upper flow control trigger level
where appropriate are defined by L2 in the table below. L1
defines the lower flow control trigger level where
applicable. Separate upper and lower flow control trigger
levels introduce a hysteresis element in in-band and out-of-
band flow control (see section 13).
Data Sheet Revision 1.2
OXFORD SEMICONDUCTOR LTD.
FCR
[7:6]
00
01
10
11
FCR[5:4]
Table 9: Transmit Interrupt Trigger Levels
00
01
10
11
FIFO Size 128
Table 10: Receiver Trigger Levels
112
L1
16
32
1
650
112
120
Transmit Interrupt Trigger level
L2
16
32
Ext. 550 / 750
FIFO Size 128
L1
1
1
1
1
Mode
112
16
32
64
112
L2
32
64
1
FIFO Size 16
n/a
n/a
n/a
n/a
L1
550
L2
14
1
4
8
In Byte mode (450 mode) the trigger levels are all set to 1.
In all cases, a receiver data interrupt will be generated (if
enabled) if the Receiver FIFO Level (‘RFL’) reaches the
upper trigger level L2.
950 Mode:
When 950 trigger levels are enabled (ACR[5]=1), more
flexible trigger levels can be set by writing to the TTL, RTL,
FCL and FCH (see section 15) hence ignoring FCR[7:6].
9
9.1
On the falling edge of a start bit, the receiver will wait for
1/2 bit and re-synchronise the receiver’s sampling clock
onto the centre of the start bit. The start bit is valid if the
SIN line is still low at this mid-bit sample and the receiver
will proceed to read in a data character. Verifying the start
bit prevents the receiver from assembling a false data
character due to a low going noise spike on the SIN input.
Once the first stop bit has been sampled, the received data
is transferred to the RHR and the receiver will then wait for
a low transition on SIN signifying the next start bit.
The receiver will continue receiving data even if the RHR is
full or the receiver has been disabled (see section 15.3) in
order to maintain framing synchronisation. The only
difference is that the received data does not get transferred
to the RHR.
9.2
The LCR specifies the data format that is common to both
transmitter and receiver. Writing 0xBF to LCR enables
access to the EFR, XON1, XOFF1, XON2 and XOFF2,
DLL and DLM registers. This value (0xBF) corresponds to
an unused data format. Writing the value 0xBF to LCR will
set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not
affected. Write the desired LCR value to exit from this
selection.
L
INE
False Start Bit Detection
Line Control Register ‘LCR’
C
ONTROL
& S
TATUS
OX16C950 rev B
Page 21