ISPLSI1048E70LQN LATTICE [Lattice Semiconductor], ISPLSI1048E70LQN Datasheet
ISPLSI1048E70LQN
Related parts for ISPLSI1048E70LQN
ISPLSI1048E70LQN Summary of contents
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Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block ...
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Functional Block Diagram Figure 1. ispLSI 1048E Functional Block Diagram I/O I/O I/O I/O I RESET GOE 0 Generic Output Routing Pool (ORP) GOE 1 Logic Blocks (GLBs I I/O 1 ...
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Absolute Maximum Ratings Supply Voltage V . ................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION A 470Ω ...
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External Timing Parameters 4 TEST 2 # PARAMETER COND. t pd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass t pd2 A 2 Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback max (Int.) ...
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External Timing Parameters 4 TEST 2 # PARAMETER COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay, Worst Case Path pd2 f max (Int Clock Frequency with Internal Feedback ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 22 I/O Register Bypass iobp t 23 I/O Latch Delay iolat t 24 I/O Register Setup Time before Clock iosu t ioh 25 I/O Register Hold Time after Clock t 26 I/O ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 22 I/O Register Bypass iobp t 23 I/O Latch Delay iolat t 24 I/O Register Setup Time before Clock iosu t 25 I/O Register Hold Time after Clock ioh t 26 I/O ...
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Internal Timing Parameters PARAMETER # Outputs t 49 Output Buffer Delay Output Slew Limited Delay Adder I/O Cell OE to Output Enabled oen t odis 52 I/O Cell OE to Output Disabled t 53 ...
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Internal Timing Parameters PARAMETER # Outputs t 49 Output Buffer Delay Output Slew Limited Delay Adder I/O Cell OE to Output Enabled oen t 52 I/O Cell OE to Output Disabled odis t 53 ...
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Timing Model I/O Cell Ded. In #28 I/O Reg Bypass I/O Pin #22 (Input) Input GRP Loading Register D Q RST #29, 31-33 #59 # Reset Distribution Y1,2,3 Y0 GOE 0 Derivations of ...
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Maximum GRP Delay vs. GLB Loads Power Consumption Power consumption in the ispLSI 1048E device depends on two primary factors: the speed at which the device is operating ...
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Pin Description NAME PQFP / TQFP PIN NUMBERS I I/O 5 21, 22, 23, I I/O 11 27, 28, 29, I I/O 17 34, 35, 36, I I/O 23 40, 41, 42, ...
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Pin Configuration ispLSI 1048E 128-Pin PQFP Pinout Diagram GND ...
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Pin Configuration ispLSI 1048E 128-Pin TQFP Pinout Diagram GND ...
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Package Thermal Characteristics For the ispLSI 1048E-125LT strongly recommended that the actual Icc be verified to ensure that the maximum junction temperature (T ) with power supplied is not J exceeded. Depending on the specific logic design and ...
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Ordering Information (Cont.) Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 125 125 100 100 90 ispLSI FAMILY fmax (MHz) tpd (ns) ispLSI 70 Revision History Date Version — 11 August 2006 12 Specifications ...