ISPLSI2032-110LJI LATTICE [Lattice Semiconductor], ISPLSI2032-110LJI Datasheet - Page 5

• Manufacturer Part Number: ISPLSI2032-110LJI
• Description: In-System Programmable High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
External Timing Parameters
PARAMETER
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
pd2
max
max (Ext.)
max (Tog.)
su1
co1
h1
su2
co2
h2
r1
rw1
ptoeen
ptoedis
goeen
goedis
wh
wl
COND.
TEST
C
C
A
A
A
A
A
B
B
–
–
–
–
–
–
–
–
–
–
4
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 Ext. Synchronous Clk Pulse Duration, High
19 Ext. Synchronous Clk Pulse Duration, Low
#
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
2 Data Prop. Delay
3 Clk Frequency with Internal Feedback
4 Clk Frequency with Ext. Feedback
5 Clk Frequency, Max. Toggle
6 GLB Reg Setup Time before Clk, 4 PT Bypass
7 GLB Reg. Clk to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clk, 4 PT Bypass
9 GLB Reg. Setup Time before Clk
2
Over Recommended Operating Conditions
DESCRIPTION
1
5
(
Specifications ispLSI 2032/A
tsu2 + tco1
3
1
)
MIN. MAX.
125
200
180
3.0
0.0
4.0
0.0
4.0
2.5
2.5
–
–
–
–
–
–
–
–
–
-180
10.0
10.0
7.5
5.0
4.0
4.5
7.0
5.0
5.0
–
–
–
–
–
–
–
–
–
–
MIN.
111
167
154
3.0
0.0
4.5
0.0
4.5
3.0
3.0
–
–
–
–
–
–
–
–
–
-150
MAX.
11.0
11.0
5.5
8.0
4.5
5.0
8.0
5.0
5.0
–
–
–
–
–
–
–
–
–
–
MIN.
137
100
167
4.0
0.0
5.5
0.0
5.0
3.0
3.0
–
–
–
–
–
–
–
–
–
-135
Table 2-0030B-180/2032
MAX.
10.0
10.0
12.0
12.0
7.5
4.5
5.5
6.0
6.0
–
–
–
–
–
–
–
–
–
–
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns