ISPLSI2032-110LJI LATTICE [Lattice Semiconductor], ISPLSI2032-110LJI Datasheet - Page 9

• Manufacturer Part Number: ISPLSI2032-110LJI
• Description: In-System Programmable High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

ispLSI 2032/A Timing Model
Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
Derivations of
Ded. In
Y0,1,2
GOE 0
I/O Pin
Reset
(Input)
t
t
t
su
h
co
2.1 ns
1.5 ns
7.7 ns
I/O Delay
#21
#20
=
=
=
=
=
=
=
=
=
=
=
=
I/O Cell
t
su,
Logic + Reg su - Clock (min)
(
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)
Clock (max) + Reg h - Logic
(
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)
Clock (max) + Reg co + Output
(
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
Reg 4 PT Bypass
io +
t
io +
#33, 34,
XOR Delays
Control
PTs
#25, 26, 27
Feedback
t
orp +
20 PT
35
t
#24
grp +
t
grp +
Comb 4 PT Bypass #23
9
RE
OE
CK
t
ob)
t
Specifications ispLSI 2032/A
ptck(min))
t
20ptxor)
GLB
1
GLB Reg Bypass
D
RST
GLB Reg
Delay
Table 2- 0042-16/2032
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2000
#38,
39
I/O Cell
(Output)
I/O Pin