ISPLSI3256A-50LM LATTICE [Lattice Semiconductor], ISPLSI3256A-50LM Datasheet - Page 3

• Manufacturer Part Number: ISPLSI3256A-50LM
• Description: In-System Programmable High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 128 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
The 128 I/O cells are grouped into eight sets of 16 bits.
Each of these I/O groups is associated with a logic
Megablock through the use of the ORP. These groups of
16 I/O cells share one Product Term Output Enable which
is associated with a specific pair of Megablocks and two
Global Output Enables.
Four Twin GLBs, 16 I/O cells and one ORP are con-
nected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
16 I/O cells by the ORP. The ispLSI 3256A device
contains eight of these Megablocks.
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal-
ized to minimize timing skew and logic glitching.
Clocks in the ispLSI 3256A device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
The table at right lists key attributes of the device along
with the number of resources available.
Description (continued)
3
An additional feature of the ispLSI 3256A is its Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device’s input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.
The ispLSI 3256A supports the full boundary scan IEEE
1149.1 specification for ISP programming and board-
level tests via the TAP controller port. It is also fully
backward compatible to the Lattice ISP interface. While
fully JEDEC file and functionally compatible with the
earlier ispLSI 3256 devices, the 3256A requires a modi-
fied Boundary Scan Description Library (BSDL) model to
support boundary scan test and programming. As a
result, existing 3256 test programs that use the boundary
scan test feature must be updated to use the 3256A.
Please contact Lattice Applications for the new model.
The ispLSI 3256A supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
Key Attributes of the ispLSI 3256A
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