ISPLSI3256A-50LM LATTICE [Lattice Semiconductor], ISPLSI3256A-50LM Datasheet - Page 8
ISPLSI3256A-50LM
Manufacturer Part Number
ISPLSI3256A-50LM
Description
In-System Programmable High Density PLD
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.ISPLSI3256A-50LM.pdf
(13 pages)
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
PARAMETER
Internal Timing Parameters
Outputs
t
t
t
t
Clocks
t
t
Global Reset
t
t
t
ob
obs
oen
odis
gy0/1/2
ioy3/4
gr
goe
toe
46 Output Buffer Delay
47 Output Buffer Delay, Slew Limited Adder
48 I/O Cell OE to Output Enabled
49 I/O Cell OE to Output Disabled
50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line
51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line
52 Global Reset to GLB and I/O Registers
53 Global OE Pad Buffer
54 Test OE Pad Buffer
#
2
Over Recommended Operating Conditions
1
DESCRIPTION
8
Specifications ispLSI 3256A
MIN. MAX.
2.7
0.7
–
–
–
–
–
–
–
-90
11.9
1.9
6.8
6.8
2.7
3.7
6.7
2.3
3.2
MIN.
3.6
1.2
–
–
–
–
–
–
–
-70
MAX.
12.4
7.1
2.4
7.2
7.2
3.6
5.2
2.8
9.8
MIN.
4.9
1.6
–
–
–
–
–
–
–
-50
MAX.
Table 2-0037C/3256A
13.3
13.2
4.9
7.0
3.3
9.8
9.8
9.6
3.7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns