GAL20LV8ZD-25QJ LATTICE [Lattice Semiconductor], GAL20LV8ZD-25QJ Datasheet - Page 15

• Manufacturer Part Number: GAL20LV8ZD-25QJ
• Description: Low Voltage, Zero Power E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

An electronic signature word is provided in every GAL20LV8ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is al-
ways available to the user independent of the state of the security
cell.
NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter checksum.
A security cell is provided in the GAL20LV8ZD devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The electronic signature data is always avail-
able to the user, regardless of the state of this security cell.
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.
Electronic Signature
Security Cell
Device Programming
15
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL20LV8ZD devices includes circuitry that allows each reg-
istered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
GAL20LV8ZD devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The GAL20LV8ZD uses pin 5 as the dedicated power-down sig-
nal to put the device in to the power-down state. DPP is an active
high signal where a logic high driven on this signal puts the device
into power-down state. Input pin 5 cannot be used as a logic func-
tion input on this device.
Output Register Preload
Input Buffers
Dedicated Power-Down Pin
Specifications GAL20LV8ZD