F25L004A-100DG ESMT [Elite Semiconductor Memory Technology Inc.], F25L004A-100DG Datasheet - Page 10

• Manufacturer Part Number: F25L004A-100DG
• Description: 4Mbit (512Kx8) 3V Only Serial Flash Memory
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.
Read (33 MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
Elite Semiconductor Memory Technology Inc.
Figure 2 : READ SEQUENCE
bottom memory type ; third byte 13H as memory capacity.
The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions
effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.
SCK
SO
CE
SI
MODE3
MODE1
MSB
1 2 3 4 5 6 7 8
HIGH IMPENANCE
03
MSB
ADD.
15 16
ADD.
23 24
ADD.
MSB
31 32
(wrap-around) of the address space, i.e. for 4Mbit density, once
the data from address location 7FFFFH had been read, the next
output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
D
N
OUT
39 40
N+1
D
OUT
47 48
N+2
D
Publication Date: Apr. 2007
OUT
55 56
Revision:
23
D
N+3
-A
OUT
0
]. CE must remain active
63 64
D
N+4
F25L004A
1.2
OUT
70
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