F25L004A-100DG ESMT [Elite Semiconductor Memory Technology Inc.], F25L004A-100DG Datasheet - Page 17

• Manufacturer Part Number: F25L004A-100DG
• Description: 4Mbit (512Kx8) 3V Only Serial Flash Memory
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A
Chip-Erase instruction will be ignored if any of the memory area
is protected. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE must remain active
low for the duration of the Chip-Erase instruction sequence. The
Chip-Erase instruction is initiated by executing an 8-bit command,
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
Figure12 : READ-STATUS-REGISTER (RDSR) SEQUENCE
Elite Semiconductor Memory Technology Inc.
CE must be driven low before the RDSR instruction is entered
FIGURE 11 : CHIP-ERASE SEQUENCE
SCK
SO
CE
SI
MODE3
MODE1
MSB
0
HIGH IMPENANCE
1
2
3
05
4
SCK
5
SO
CE
SI
MODE0
MODE3
6
7
MSB
MSB
HIGH IMPENANCE
Bit7
60H or C7H. CE must be driven high before the instruction is
executed. The user may poll the Busy bit in the software status
register or wait T
Chip-Erase cycle.
See Figure 11 for the Chip-Erase sequence.
and
Read-Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE
See Figure 12 for the RDSR instruction sequence.
0 1 2 3 4 5 6 7
8
60 or C7
Bit6
remain
9
Bit5
10
Register Out
Bit4
low
CE
11
Status
for the completion of the internal self-timed
Bit3
12
until
Publication Date: Apr. 2007
Bit2
13
Revision:
the
Bit1
14
status
Bit0
F25L004A
1.2
data
17/32
is
read.