F25L004A-100DG ESMT [Elite Semiconductor Memory Technology Inc.], F25L004A-100DG Datasheet - Page 18

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F25L004A-100DG

Manufacturer Part Number
F25L004A-100DG
Description
4Mbit (512Kx8) 3V Only Serial Flash Memory
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
ESMT
F25L004A
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
MODE0
06
SI
MSB
HIGH IMPENANCE
SO
FIGURE 13 : WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch
bit and AAI bit to 0 disabling any new Write operations from occurring.
CE must be driven high before the WRDI instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
MODE0
04
SI
MSB
HIGH IMPENANCE
SO
Figure 14 : WRITE DISABLE (WRDI) SEQUENCE
Publication Date: Apr. 2007
Elite Semiconductor Memory Technology Inc.
Revision:
1.2
18/32

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