HD64336901G Renesas Technology, HD64336901G Datasheet - Page 289
HD64336901G
Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
1.HD64336901G.pdf
(408 pages)
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16.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
16.4.1
In single mode, A/D conversion is performed once for the analog input on the specified single
channel as follows:
1.
2.
3.
4.
16.4.2
In scan mode, A/D conversion is performed sequentially for the analog input on the specified
channels (four channels maximum) as follows:
1. When the ADST bit is set to 1 by software, or external trigger input, A/D conversion starts on
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.
4. The ADST bit is not automatically cleared to 0. Steps [2] to [3] are repeated as long as the
the first channel in the group.
the A/D data register corresponding to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
A/D conversion is started from the first channel when the ADST bit in ADCSR is set to 1,
according to software or external trigger input.
When A/D conversion is completed, the result is transferred to the corresponding A/D data
register to the channel.
On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the
ADST bit is automatically cleared to 0 and the A/D converter enters the wait state.
Single Mode
Scan Mode
Operation
Rev. 1.00, 11/03, page 261 of 376
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