HD64336901G Renesas Technology, HD64336901G Datasheet - Page 64

• Manufacturer Part Number: HD64336901G
• Description: (HD64xxx Series) 16-BIT MICROCONTROLLER
• Manufacturer: Renesas Technology

2.6
CPU operation is synchronized by a system clock ( ). The period from a rising edge of to the
next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Rev. 1.00, 11/03, page 36 of 376
Basic Bus Cycle
Access to On-Chip Memory (RAM, ROM)
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Figure 2.9 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Write data
Read data
T
2
state