24C01C MicrochipTechnology, 24C01C Datasheet - Page 9

• Manufacturer Part Number: 24C01C
• Description: 1K5.0VI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

8.0
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1
The 24C01C contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the 24C01C issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24C01C discontinues transmission (Figure 8-1).
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C01C as part of a write operation. After the word
FIGURE 8-1:
FIGURE 8-2:
FIGURE 8-3:
1997 Microchip Technology Inc.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
READ OPERATIONS
Current Address Read
Random Read
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CURRENT ADDRESS READ
RANDOM READ
SEQUENTIAL READ
CONTROL
BYTE
S
T
A
R
T
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
CONTROL
BYTE
DATA n
A
C
K
S
T
A
R
T
S
ADDRESS (n)
A
C
K
Preliminary
WORD
CONTROL
DATA n + 1
BYTE
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24C01C will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C01C dis-
continues transmission (Figure 8-2). After this com-
mand, the internal address counter will point to the
address location following the one that was just read.
8.3
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C01C transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24C01C to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24C01C contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 7F to address 00.
A
C
K
S
T
A
R
T
S
A
C
K
A
C
K
CONTROL
Sequential Read
BYTE
DATA n + 2
DATA
A
C
K
O
N
A
C
K
A
C
K
S
T
O
P
P
DATA (n)
DATA n + X
24C01C
N
O
C
A
K
DS21201A-page 9
S
T
O
P
P
N
O
A
C
K
P
S
T
O
P