24LC65-IP MicrochipTechnology, 24LC65-IP Datasheet - Page 5

• Manufacturer Part Number: 24LC65-IP
• Description: 64K2.5VI2CSmartSerialEEPROM
• Manufacturer: MicrochipTechnology

3.6
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code, for the 24LC65 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte defines
the operation to be performed. When set to a one a
read operation is selected, when set to a zero a write
operation is selected. The next two bytes received
define the address of the first data byte (Figure 4-1).
Because only A12..A0 are used, the upper three
address bits must be zeros. The most significant bit of
the most significant byte is transferred first. Following
the start condition, the 24LC65 monitors the SDA bus
checking the device type identifier being transmitted.
Upon receiving a 1010 code and appropriate device
select bits, the slave device (24LC65) outputs an
acknowledge signal on the SDA line. Depending upon
the state of the R/W bit, the 24LC65 will select a read
or write operation.
FIGURE 3-2:
FIGURE 4-1:
SDA LINE
Operation Control Code
BUS ACTIVITY
MASTER
BUS ACTIVITY
1996 Microchip Technology Inc.
Read
Write
1
START
Device Addressing
0
SLAVE ADDRESS
1
CONTROL BYTE
ALLOCATION
BYTE WRITE
1010
1010
S
S
T
A
R
T
0
Device Address
Device Address
CONTROL
Device Select
A2
BYTE
READ/WRITE
A1
R/W
A0
R/W
A
C
K
A
1
0
0 0 0
ADDRESS
WORD
4.0
4.1
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low is placed onto the bus
by the master transmitter. This indicates to the
addressed slave receiver (24LC65) that a byte with a
word address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore
the next byte transmitted by the master is the high-order
byte of the word address and will be written into the
address pointer of the 24LC65. The next byte is the
least significant address byte. After receiving another
acknowledge signal from the 24LC65 the master device
will transmit the data word to be written into the
addressed memory location. The 24LC65 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24LC65 will not generate acknowledge
signals (Figure 4-1).
4.2
The write control byte, word address and the first data
byte are transmitted to the 24LC65 in the same way as
in a byte write. But instead of generating a stop condi-
tion the master transmits up to eight pages of eight data
bytes each (64 bytes total) which are temporarily stored
in the on-chip page cache of the 24LC65. They will be
written from the cache into the EEPROM array after the
master has transmitted a stop condition. After the
receipt of each word, the six lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remain con-
stant. If the master should transmit more than eight
bytes prior to generating the stop condition (writing
across a page boundary), the address counter (lower
three bits) will roll over and the pointer will be incre-
mented to point to the next line in the cache. This can
continue to occur up to eight times or until the cache is
full, at which time a stop condition should be generated
by the master. If a stop condition is not received, the
cache pointer will roll over to the first line (byte 0) of the
cache, and any further data received will overwrite pre-
viously captured data. The stop condition can be sent
at any time during the transfer. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin. The 64 byte cache will con-
tinue to capture data until a stop condition occurs or the
operation is aborted (Figure 4-2).
WRITE OPERATION
Byte Write
Page Write
A
C
K
DATA
24LC65
DS21073E-page 5
A
C
K
P
S
T
O
P