M36W432BG ST Microelectronics, M36W432BG Datasheet - Page 40

• Manufacturer Part Number: M36W432BG
• Description: 32 Mbit 2Mb x16 / Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM / Multiple Memory Product
• Manufacturer: ST Microelectronics

M36W432TG, M36W432BG
SRAM OPERATIONS
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable, W
put Enable, G
V
inputs, UB
Valid data will be available on the output pins after
a time of t
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
er than the address. Data out may be indetermi-
nate at t
will always be valid at t
23, Figures 17 and 18, SRAM Read AC Character-
istics).
Write. Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
W
the Chip Enable inputs, E1
Enable input, W
dress transitions for subsequent write cycles.
A Write operation is initiated when E1
E2
on the falling edge of E1
or the falling edge of W
The Write cycle is terminated on the rising edge of
E1
E2
40/66
IL
S
S
S
S
, Chip Enable, E2
, the rising edge of W
, whichever occurs first.
and E1
is at V
E1LQX
AVQV
S
IH
S
and LB
and W
are at V
S
, t
, is at V
after the last stable address. If the
S
E2HQX
, must be deasserted during ad-
S
S
E1LQV
S
are at V
is at V
IL
, is at V
AVQV
IL
, and E2
and t
S
, Chip Enable, E1
S
, whichever occurs last.
, t
, the rising edge of E2
S
S
E2HQV
IL
or the falling edge of
and E2
(see Table 23, Table
GLQX
IL
. The data is latched
IH
.
, and Byte Enable
S
S
, or t
is at V
, but data lines
, is at V
S
, or the Write
GLQV
S
IH
is at V
IH
. Either
S
) rath-
, Out-
, is at
IL
S
,
If the Output is enabled (E1
G
pedance within t
be taken to avoid bus contention in this type of op-
eration. The Data input must be valid for t
fore the rising edge of Write Enable, for t
before the rising edge of E1
the falling edge of E2
remain valid for t
24, SRAM Write AC Characteristics, Figures 20,
21, 22 and 23).
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 23,
SRAM Read AC Characteristics, Figure 19, SRAM
Standby AC Waveforms). The SRAM is in Standby
mode whenever either Chip Enable is deasserted,
E1
UB
Data Retention. The SRAM data retention per-
formance as V
scribed in Table 25, SRAM Low V
Retention Characteristic, and Figure 24, SRAM
Low V
UB
tion mode, the minimum standby current mode is
entered when E1
or E2
tention mode, minimum standby current mode is
entered when E2
Output Disable. The data outputs are high im-
pedance when the Output Enable, G
with Write Enable, W
S
S
=V
S
S
at V
/ LB
and LB
S
IL
DDS
), then W
S
IH
V
Controlled. In E1
Data Retention AC Waveforms, E1
DDS
or E2
S
are at V
– 0.2V. In E2
DDS
WLQZ
S
WHDX
S
S
S
will return the outputs to high im-
at V
S
goes down to V
0.2V.
V
S
of its falling edge. Care must
, t
IH
, whichever occurs first, and
, at V
DDS
IL
E1HAX
.
. It is also possible when
– 0.2V and E2
S
IH
S
controlled data reten-
S
S
.
or t
or for t
=V
controlled data re-
E2LAX
IL
, E2
DVE2L
DR
S
S
(see Table
, is at V
DDS
=V
DVWH
S
are de-
IH
before
DVE1H
Data
0.2V
S
and
be-
or
IH