X3100 Xicor, X3100 Datasheet
X3100
Related parts for X3100
X3100 Summary of contents
Page 1
... Flexible Power Management with 1µA Sleep Mode • Cell Balancing Control DESCRIPTION The X3100 is a protection and monitor IC for use in battery packs consisting of 4 series Lithium-Ion battery cells. The X3101 is designed to work in 3 cell applications. Both devices provide internal over- ...
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... Second, in Monitor mode, a microcontroller with A/D converter measures battery cell voltage and pack current via pin AO and the X3100 or X3101 on-board MUX. The user can thus implement protection, charge/discharge, cell balancing or gas gauge software algorithms to suit the specific application and characteristics of the cells used ...
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... Over-charge Voltage Protection/Load Monitor (OVP/LMON): This one pin performs two functions depending upon the present mode of operation of the X3100 or X3101. —Over-charge Voltage Protection (OVP) This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, ...
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... FET and discharge FET are OFF. Power to the X3100 or X3101 is applied to pin VCC via diodes D6 and D7. These diodes allow the device to be REV 1.1.8 12/10/02 powered by the Li-Ion battery cells in normal operating ...
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... X3100/X3101 – Preliminary Information Figure 1. Typical Application Circuit REV 1.1.8 12/10/02 www.xicor.com Characteristics subject to change without notice ...
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... V applied to the VCC pin, as would be the case during a battery charge condition. (See Figure 2.) When V (AS2-AS0) and the SPI communication pins (CS, CLK, SI, SO) must be low, so the X3100 and X3101 power up – OFF via 6 9 correctly into the normal operating mode. This can be done by using a power-on reset circuit ...
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... V Tuned to 5V±0.5% RGO 2ms (Typ X3100/1 in Over-Current Protection Mode 0 = X3100/1 NOT in Over-Current Protection Mode X3100/1 in Over-Current Protection Mode OR VRGO Not Yet Tuned 0 = X3100/1 NOT in Over-Current Protection Mode AND VRGO Tuned T +200ms < V CELL > V CELL ...
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... X3100/X3101 – Preliminary Information CONFIGURATION REGISTER The X3100 and X3101 can be configured for specific user requirements using the Configuration Register. Table 1. Configuration Register Functionality Bit(s) Name 0-5 – (don’t care) Switch Cell Charge Enable 6 SWCEN threshold function ON/OFF ...
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... EEPROM into the SRAM configuration register upon power-up (Figure 3 the case that the X3100 or X3101 is configured for use with only three Li-Ion battery cells (i.e. CELLN=0), then VCELL4 (pin 7) MUST be tied to Vss (pin 9) to ensure correct operation. ...
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... Write to 15 4kbit EEPROM Sleep Control (SLP) Power Down Setting the SLP bit to ‘1’ forces the X3100 or X3101 into Power Up the sleep mode Mode” on page 15. Table 13. Sleep Mode Selection Configuration Register (SRAM=New Value) Control Register Bits ...
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... CB1–CB4 can be controlled by using the WCNTR In- struction to set bits CBC1–CBC4 in the control register (Table 16). STATUS REGISTER The status of the X3100 or X3101 can be verified by using the RDSTAT command to read the contents of the Status Register (Table 17). Table 17. Status Register ...
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... If the cell charge enable function is switched OFF (configuration bit SWCEN=1), then bit 2 of the status register effectively only represents information about the over-charge status (OVDS) of the X3100 or X3101 (See Table 18, Table 17 and Figure 2). Case Status V ...
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... Over- current monitoring is continuous. In monitor mode (see page 20) over-charge and over-discharge monitoring is also continuous. Over-charge Protection The X3100 and X3101 monitor the voltage on each battery cell ( for any cell, V CELL time exceeding T , then the Charge FET will be ...
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... The device has now entered over-charge protection mode. While in over-charge protection mode: — The battery cells are permitted to discharge via the discharge FET, and diode D — The X3100 or X3101 monitors the voltages V (2,3) below the “Return from over-charge threshold” (V — (It is possible to change the status of UVP/OCP or OVP/LMON using the control register) — ...
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... OVPC in the control register is also prohibited. The device returns from sleep mode when V (e.g. when the battery terminals are connected to a battery charger). In this case, the X3100 or the X3101 restores the 5VDC regulated output (section “Voltage Regulator” on page 21), and communication via the SPI port resumes ...
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... X3100/X3101 – Preliminary Information Figure 6. Over-discharge Protection Mode—Event Diagram VCC VCELL V UV UVP/OCP OVP/LMON RGO Event 0 Note 1: If SWEN=0 and V < then OVP/LMON stays high and charging is prohibited. CELL CE Note 2: OVP/LMON stays high until the microcontroller writes a “1” to the OVPC bit in the control register. This sets the signal low, which turns on the charge FET. It cannot be turned on prior to this time. Note 3: UVP/OCP stays high until the microcontroller writes a “ ...
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... The internal over-discharge release timer continues counting for t (4,5) — The X3100/X3101 should be in monitor mode (AS2:AS0 not all low) for recovery time based on t wise recovery is based on two successive samples about 120ms apart. — The internal over-discharge release timer times out, AND V — ...
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... The 5VDC voltage regulator output (V active during an over-current protection mode. Once the device enters over-current protection mode, the X3100 and X3101 begin a load monitor state. In the load monitor state, a small current (I passed out of pin OVP/LMON in order to determine the load resistance. The load resistance is the impedance seen looking out of pin OVP/LMON, between terminal P+ and pin VSS (See Figure 7 ...
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... It is possible to change the status of UVPC and OVPC in the control register, although the status of pins UVP/OCP and OVP/LMON will not change until the device has returned from over-current protection mode. — The X3100/X3101 now continuously monitors the load resistance to detect whether or not an over- (2,3) current condition is still present across the battery terminals P+/P-. ...
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... VCS2–VCS Notes: (1) This is the normal state of the X3100 or X3101. While in this state Over-charge and Over-discharge Protection conditions are periodically monitored (See “Periodic Pro- tection Monitoring” on page 12.) (2) VCS , VCS are read at AO with respect bias ...
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... OP1 in turn drives the regulator pnp transistor (Q1). The negative feedback at the regulator output maintains the voltage at 5VDC±0.5% (including ripple) despite changes in load, and differences in regulator transistors. When power is applied to pin VCC of the X3100 or X3101 regulated to 5VDC±10% for a nominal RGO time of T +2ms ...
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... The SI pin carries the input signal and SO provides the output signal. SCK clocks data in or out. The X3100 and X3101 operate in SPI mode 0 which requires SCK to be normally low when not transferring data. It also specifies that the rising edge of SCK clocks data into the device, while the falling edge of SCK clocks data out ...
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... X3100/X3101 – Preliminary Information Table 30. X3100/X3101 Instruction Set Instruction Instruction Name Format* WREN 0000 0110 WRDI 0000 0100 EEWRITE 0000 0010 EEREAD STAT 0000 0101 EEREAD 0000 0011 WCFIG 0000 1001 WCNTR 0000 1010 RDSTAT 0000 1011 SET IDL 0000 0001 *Instructions have the MSB in leftmost position and are transferred MSB first ...
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... LOW and remain LOW for the duration of the operation. The host may continue to write bytes of data to the X3100 or X3101. The only restriction is the 16 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “ ...
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... X3100/X3101 – Preliminary Information Figure 13. EEPROM Page Write (EEWRITE) Operation Sequence SCK EEWRITE Instruction SCK Data Byte Figure 14. EEPROM Read Status (EEREAD STAT) Operation Sequence SCK EEREAD STAT Instruction ...
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... EEPROM Read Sequence (EEREAD) When reading from the X3100 or X3101 EEPROM memory first pulled LOW to select the device. The 8- bit EEREAD instruction is transmitted to the X3100 or X3101, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] specifi zeroes). After ...
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... X3100/X3101 – Preliminary Information Write Configuration Register (WCFIG) The Write Configuration Register (WCFIG) instruction updates the static part of the Configuration Register. These new values take effect immediately, for example writing a new Over-discharge voltage limit. However, to make these changes permanent, so they remain if the ...
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... SO REV 1.1.8 12/10/02 Set ID Lock (SET IDL) The contents of the EEPROM memory array in the X3100 or X3101 can be locked in one of eight configurations using the SET ID lock command. When a section of the EEPROM array is locked, the contents cannot be changed, even when a valid write operation attempts a write to that area. The SET IDL command operation is shown in Figure 19 ...
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... X3100/X3101 – Preliminary Information ABSOLUTE MAXIMUM RATINGS Symbol Storage temperature Operating temperature DC output current Lead temperature (soldering 10 seconds) VCC Power supply voltage VCELL Cell voltage Terminal voltage (Pins: SCK, SI, SO, CS, AS0, AS1, AS2, VCS1, V TERM1 VCS2, OVT, UVT, OCT, AO) V Terminal voltage (VCELL1) ...
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... X3100/X3101 – Preliminary Information OPERATING CHARACTERISTICS X3100 (Over the recommended operating conditions unless otherwise specified) Description 5V regulated voltage 5VDC voltage regulator current limit V supply current ( supply current ( supply current ( supply current ( supply current (5) CC Cell over-charge protection mode ...
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... X3100/X3101 – Preliminary Information Description Over-current mode detection voltage (Default in Boldface) Over-current mode detection time Over-current mode release time Load resistance over-current mode release condition Cell charge threshold voltage X3100 wake-up voltage (For Vcc above this voltage, the device wakes up) ...
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... X3100/X3101 – Preliminary Information OPERATING CHARACTERISTICS X3101 (Over the recommended operating conditions unless otherwise specified) Description 5V regulated voltage 5VDC voltage regulator current limit I V supply current ( supply current ( supply current ( supply current ( supply current (5) CC Cell over-charge protection mode ...
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... X3100/X3101 – Preliminary Information Description Over-current mode detection voltage (Default in Boldface) Over-current mode detection time Over-current mode release time Load resistance over-current mode release condition Cell charge threshold voltage X3100 wake-up voltage (For Vcc above this voltage, the device wakes up) ...
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... X3100/X3101 – Preliminary Information POWER-UP TIMING Symbol (6) t Power-up to SPI read operation (RDSTAT, EEREAD STAT) PUR (6) t Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR) PUW1 (6) t Power-up to SPI write operation (WCNTR - bits 10 and 11) PUW2 Notes: ( and t ...
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... X3100/X3101 – Preliminary Information A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) SERIAL INPUT TIMING Symbol Parameter f Clock frequency SCK t Cycle time CYC t CS lead time LEAD t CS lag time LAG t Clock HIGH time WH t Clock LOW time WL t Data setup time ...
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... X3100/X3101 – Preliminary Information Serial Output Timing Symbol Parameter f Clock Frequency SCK t Output Disable Time DIS t Output Valid from Clock LOW V t Output Hold Time HO (11) t Output Rise Time RO (11) t Output Fall Time FO Notes: (11)This parameter is not 100% tested. Serial Output Timing ...
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... X3100/X3101 – Preliminary Information Analog Output Response Time Symbol t AO Output Stabilization Time (Voltage Source Change) VSC t AO Output Stabilization Time (Current Sense Gain Change) CSGO Control Outputs Response Time (UVP/OCP, OVP/MON, CB4 CB3, CB2, CB1, RGC) ANALOG OUTPUT RESPONSE TIME ...
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... Load 50mA Load www.xicor.com Monitor Mode Current 450 400 350 300 - Tem perature X3100 Over Discharge Trip Voltage (Typical) -25 25 Temperature (Deg C) 1.95V Setting 2.05V Setting 2.15V Setting 2.25V Setting Voltage Regulator Output (Typical) Vcc = 10.8V to 16V Ohm (I = 200mA) ...
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... X3100/X3101 – Preliminary Information .026 (.65) BSC .377 (9.60) .385 (9.80) .0075 (.19) .0118 (.30) 0° – 8° .020 (.50) .030 (.75) Detail A (20X) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.8 12/10/02 28-Lead Plastic, TSSOP, Package Code V28 .169 (4.3) .252 (6.4) BSC .177 (4.5) .047 (1.20) .002 (.06) ...
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... X3100/X3101 – Preliminary Information ORDERING INFORMATION Device LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fi ...