X3100 Xicor, X3100 Datasheet - Page 17

• Manufacturer Part Number: X3100
• Description: 3 or 4 Cell Li-Ion Battery Protection and Monitor IC
• Manufacturer: Xicor

X3100/X3101 – Preliminary Information
REV 1.1.8 12/10/02
Table 22. Over-discharge Protection Mode—Event Diagram Description (Continued)
Event
(2,3)
(3,4)
(4,5)
[3]
[4]
[5]
While device is in sleep (in over-discharge protection) mode:
Return from sleep mode (but still in over-discharge protection mode):
If the cell charge enable func-
If the cell charge enable func-
Charge enable function is
— The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA.
— The output of the 5VDC voltage regulator (RGO) is 0V.
— Access to the X3100/X3101 via the SPI port is NOT possible.
— Vcc rises above the “Return from Sleep mode threshold Voltage” (V
— Power is returned to ALL internal circuitry
— 5VDC output is returned to the regulator output (RGO).
— Access is enabled to the X3100/X3101 via the SPI port.
— The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control reg-
— The voltage of all of the battery cells (V
— The internal Over-discharge release timer begins counting down.
— The X3100/X3101 is still in over-discharge protection mode.
— The internal over-discharge release timer continues counting for t
— The X3100/X3101 should be in monitor mode (AS2:AS0 not all low) for recovery time based on t
— The internal over-discharge release timer times out, AND V
— The device returns from over-discharge protection mode, and is now in normal operation mode.
— The Charger voltage can now drop below VSLR and the X3100/X3101 will not go back to sleep.
— The discharge FET is can now be switched ON (UVP/OCP=V
— The status of the charge FET remains unaffected (ON)
— The battery cells continue to receive charge via the charge FET and discharge FET (both ON).
case that the battery pack was connected to a charger. The X3100/X3101 is now powered via P+/P-, and
not the battery pack cells.
ister, although it will have no effect at this time).
wise recovery is based on two successive samples about 120ms apart.
the UVPC bit of the control register.
tion is switched ON
tion is switched ON
AND V
switched OFF
V
CELL
AND
CELL
OR
< V
> V
CE
CE
— The X3100/X3101 initiates a reset operation that takes the longer of
— The charge FET is switched On (OVP/LMON=Vss) by the microcontroller by
— The battery cells now receive charge via the charge FET and diode D1 across
— The X3100/X3101 monitors the V
— Charge/discharge of the battery cells via P+ is no longer permitted (Charge
— (Charging may re-commence only when the Cell Charge Enable function is
T
during this time.
writing a “1” to the OVPC bit in the control register.
the discharge FET (which is OFF).
has risen above V
FET and discharge FET are held OFF).
switched OFF - See Sections: “Configuration Register” page 4, and “Sleep
mode” page 17.)
OV
+200ms or T
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CELL
Event Description
), have risen above V
UV
UVR
+200ms to complete. Do not write to the FET control bits
.
CELL
SS
CELL
) by the microcontroller by writing a “1” to
is still above V
UVR
UVR
SLR
Characteristics subject to change without notice.
voltage to determine whether or not it
.
seconds.
)—This would normally occur in the
UVR.
UVR
. Other-
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