ADP3302AR2 Analog Devices, ADP3302AR2 Datasheet - Page 8

• Manufacturer Part Number: ADP3302AR2
• Description: High Precision anyCAP Dual Low Dropout Linear Regulator
• Manufacturer: Analog Devices

Phase One: When the input voltage is equal to 3.7 V or higher,
the ADP3000 is off and the ADP3302 operates on its own to
regulate the output voltage. At this phase, current is flowing into
the input pins of the ADP3302 via the inductor L1 and the
Schottky diode. At the same time, the ADP3000 is set into sleep
mode by pulling the FB pin (via R9 and R10 resistor divider
network) to about 10% higher than its internal reference which
is set to be 1.245 V.
Phase Two: As the input voltage drops below 3.7 V, the
decreasing input voltage causes the voltage of the FB pin to be
within 5% of the 1.245 V reference. This triggers the ADP3000
to turn on, providing a 3.4 V regulated output to the inputs of
the ADP3302. The ADP3000 continues to supply the 3.4 V
regulated voltage to the ADP3302 until the input voltage drops
below 2.5 V.
Phase Three: When the input voltage drops below 2.5 V, the
ADP3302 will shut down and the ADP3000 will go into sleep
mode. With the input voltage below 2.5 V, the resistor divider
network, R1 and R2, applies a voltage that is lower than the
ADP3000’s internal 1.245 V reference voltage to the SET pin.
This causes the A
causes the ADP3302 to go into shutdown directly and Q1 to
turn on and pull the FB pin 10% or higher than the internal
1.245 V reference voltage. With the FB pin pulled high, the
ADP3000 goes into sleep mode.
Refer to Figure 20. R9 and R10 set the output voltage of the
ADP3000. R1, R2, and R3 set the shutdown threshold voltage
for the circuit. For further details on the ADP3000, please refer
to the ADP3000 data sheet.
ADP3302
Figure 21. Typical Efficiency of the Circuit of Figure 20
80
75
70
65
2.5V
2.6
4.2V
O
C1
pin to have a voltage close to 0 V, which
3.0
I
100µF
10V
AVX-TPS
O
Figure 20. Cell Li-Ion to 3 V/200 mA Converter with Shutdown at V
= 50mA + 50mA
100k
90k
R1
R2
3.4
I
O
1M
= 100mA + 100mA
R3
120k
R4
SET
A
O
GND SW2
ADP3000
I
3.8
LIM
SHDN IQ = 500µA
V
IN
SW1
AT V
FB
IN
4.2
2.5V
33nF
R5
330k
R6
100k
C2
V
(V)
IN
Q1
2N2907
R8
10k
R7
90k
–8–
Supply Sequencing Circuit
Figure 22 shows a simple and effective way to achieve sequenc-
ing of two different output voltages, 3.3 V and 5 V, in a mixed
supply voltage system. In most cases, these systems need careful
sequencing for the supplies to avoid latchup.
At turn-on, D1 rapidly charges up C1 and enables the 5 V out-
put. After a R2-C2 time constant delay, the 3.3 V output is
enabled. At turn-off, D2 quickly discharges C2 and R3 pulls
SD1 low, turning off the 3.3 V output first. After a R1-C1 time
constant delay, the 5 V output turns off.
Figure 22. Turn-On/Turn-Off Sequencing for Mixed Supply
Voltages
V
3.3V
IN
6.6µF
(SUMIDA–CDRH62)
IN5817
348k
200k
= 6V TO 12V
L1
ON/OFF
R10
1%
1%
R9
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
D1
D2
C3
100µF
10V
AVX-TPS
PIN 1
Dimensions shown in inches and (mm).
0.01µF
0.01µF
0.1968 (5.00)
0.1890 (4.80)
0.0500
(1.27)
BSC
8
1
OUTLINE DIMENSIONS
220k
1µF
C1
C2
R1
C5
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
IN
IN
SD
5
4
ADP3302
330k
8-Pin SOIC
0.2440 (6.20)
0.2284 (5.80)
D3
GND
220k
R3
(SO-8)
IN
R2
< 2.5 V
V
V
0.0098 (0.25)
0.0075 (0.19)
O2
O2
8
5
6
7
IN
IN
SD1
SD2
ADP3302
GND
ERR
2
3
OUT2
OUT1
1µF
6V
(MLC)
1µF
6V
(MLC)
8
0
0.0196 (0.50)
0.0099 (0.25)
C5
C4
1
4
0.0500 (1.27)
0.0160 (0.41)
3V
100mA
3V
100mA
C3
0.5µF
C4
0.5µF
x 45
REV. 0
V
V
5.0V
3.3V
OUT1
OUT2