T89C51CC01 Atmel, T89C51CC01 Datasheet - Page 133

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T89C51CC01

Manufacturer Part Number
T89C51CC01
Description
Enhanced 8-Bit Microcontroller
Manufacturer
Atmel
Datasheet

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Analog-to-Digital
Converter (ADC)
Features
ADC Port 1 I/O Functions
VAREF
4129K–CAN–01/05
This section describes the on-chip 10 bit analog-to-digital converter of the
T89C51CC01. Eight ADC channels are available for sampling of the external sources
AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from
the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit
cascaded potentiometric ADC.
Two modes of conversion are available:
- Standard conversion (8 bits).
- Precision conversion (10 bits).
For the precision conversion, set bit PSIDLE in ADCON register and start conversion.
The device is in a pseudo-idle mode, the CPU does not run but the peripherals are
always running. This mode allows digital noise to be as low as possible, to ensure high
precision conversion.
For this mode it is necessary to work with end of conversion interrupt, which is the only
way to wake the device up.
If another interrupt occurs during the precision conversion, it will be served only after
this conversion is completed.
Port 1 pins are general I/O that are shared with the ADC channels. The channel select
bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The
remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alter-
nate function that is available.
A conversion launched on a channel which are not selected on ADCF register will not
have any effect.
VAREF should be connected to a low impedance point and must remain in the range
specified in Table 122. If the ADC is not used, it is recommended to connect VAREF to
VAGND.
8 channels with multiplexed inputs
10-bit cascaded potentiometric ADC
Conversion time 16 micro-seconds (typ.)
Zero Error (offset)
Positive External Reference Voltage Range (VAREF) 2.4 to 3.0 Volt (typ.)
ADCIN Range 0 to 3Volt
Integral non-linearity typical 1 LSB, max. 2 LSB
Differential non-linearity typical 0.5 LSB, max. 1 LSB
Conversion Complete Flag or Conversion Complete Interrupt
Selectable ADC Clock
±
2 LSB max
T89C51CC01
133

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