T89C51CC01 Atmel, T89C51CC01 Datasheet - Page 32
T89C51CC01
Manufacturer Part Number
T89C51CC01
Description
Enhanced 8-Bit Microcontroller
Manufacturer
Atmel
Datasheet
1.T89C51CC01.pdf
(170 pages)
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T89C51CC01
Reset Value = X00X 1100b
Not bit addressable
Table 20. AUXR1 Register
AUXR1 (S:A2h)
Auxiliary Control Register 1
Reset Value = XXXX 00X0b
Note:
Number
Number
Bit
Bit
7-6
7
5
4
3
2
1
0
-
1
0
1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming
section.
Mnemonic Description
Mnemonic Description
ENBOOT
EXTRAM
DPS
GF3
Bit
Bit
A0
6
-
0
-
-
-
(1)
Internal/External RAM (00h - FFh)
access using MOVX @ Ri/@ DPTR
0 - Internal XRAM access using MOVX @ Ri/@ DPTR.
1 - External data memory access.
Disable/Enable ALE)
0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used)
1 - ALE is active only during a MOVX or MOVC instruction.
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Enable Boot Flash
Set this bit for map the boot Flash between F800h -FFFFh
Clear this bit for disable boot Flash.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
General-purpose Flag 3
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
Reserved for Data Pointer Extension.
Data Pointer Select Bit
Set to select second dual data pointer: DPTR1.
Clear to select first dual data pointer: DPTR0.
ENBOOT
5
4
-
GF3
3
2
0
1
-
4129K–CAN–01/05
DPS
0
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