T89C51CC01 Atmel, T89C51CC01 Datasheet - Page 40

• Manufacturer Part Number: T89C51CC01
• Description: Enhanced 8-Bit Microcontroller
• Manufacturer: Atmel

Overview of FM0
Operations
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
Launching Programming
40
T89C51CC01
The CPU interfaces to the Flash memory through the FCON register and AUXR1
register.
These registers are used to:
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latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 25. A MOVC instruction is then used for reading these spaces.
Table 25. FM0 Blocks Select Bits
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 26 summarizes the memory
spaces to program according to FMOD1:0 bits.
Map the memory spaces in the adressable space
Launch the programming of the memory spaces
Get the status of the Flash memory (busy/not busy)
FMOD1
0
0
1
1
FMOD0
0
1
0
1
FM0 Adressable space
User (0000h-7FFFh)
Extra Row(FF80h-FFFFh)
Hardware Security Byte (0000h)
Reserved
4129K–CAN–01/05