T89C51CC01 Atmel, T89C51CC01 Datasheet - Page 21

• Manufacturer Part Number: T89C51CC01
• Description: Enhanced 8-Bit Microcontroller
• Manufacturer: Atmel

Power Management
Reset Pin
At Power-up (Cold Reset)
4129K–CAN–01/05
Two power reduction modes are implemented in the T89C51CC01: the Idle mode and
the Power-down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynami-
cally divided by 2 using the X2 Mode detailed in Section “Clock”.
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a
high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of
the internal registers like SFRs, PC, etc. and to unpredictable behavior of the microcon-
troller. A warm reset can be applied either directly on the RST pin or indirectly by an
internal reset source such as a watchdog, PCA, timer, etc.
Two conditions are required before enabling a CPU start-up:
•
•
If one of these two conditions are not met, the microcontroller does not start correctly
and can execute an instruction fetch from anywhere in the program space. An active
level applied on the RST pin must be maintained until both of the above conditions are
met. A reset is active when the level VIH1 is reached and when the pulse width covers
the period of time where VDD and the oscillator are not stabilized. Two parameters have
to be taken into account to determine the reset pulse width:
•
•
To determine the capacitor the highest value of these two parameters has to be chosen.
The reset circuitry is shown in Figure 7.
Figure 7. Reset Circuitry
Table 14 and Table 15 give some typical examples for three values of VDD rise times,
two values of oscillator start-up time and two pull-down resistor values.
Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor
Note:
VDD must reach the specified VDD range,
The level on xtal1 input must be outside the specification (VIH, VIL).
VDD rise time (vddrst),
Oscillator startup time (oscrst).
oscrst/vddrst
20ms
These values assume VDD starts from 0v to the nominal value. If the time between two
on/off sequences is too fast, the power-supply de coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
5ms
VDD
Crst
2.7µF
10µF
1ms
RST pin
Rrst
Reset input circuitry
4.7µF
10ms
15µF
Internal reset
T89C51CC01
0
100ms
47µF
47µF
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