ST72T311 ST Microelectronics, ST72T311 Datasheet
ST72T311
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ST72T311 Summary of contents
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... September 1999 8-BIT MCU WITH 8 TO 16K OTP/EPROM, PSDIP42 PSDIP56 TQFP64 (See ordering information at the end of datasheet) Notes: 1. One only on Timer Six channels only for ST72T311J. ST72T311J4 ST72T311N2 16K 8K 512 (256) 384 (256 5.5 V 8MHz max (16MHz oscillator) - 4MHz max over 85 C ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... CPU, program memo- ry (OTP/EPROM (ST72T311N (ST72T311J) I/O lines, a Low Voltage Detector (LVD) and the following on-chip peripherals: Analog-to-Digital converter (ADC) with 8 (ST72T311N (ST72T311J) multiplexed analog inputs, industry standard synchronous SPI and asynchronous SCI serial interfaces, digital ...
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... OCMP1_A/PF4 PA7 ICAP1_A/PF6 PA6 EXTCLK_A/PF7 PA5 PC0/OCMP2_B PA4 PC1/OCMP1_B V SS_1 PC2/ICAP2_B V D D_1 PC3/ICAP1_B PA3 PC4/MISO PA2 PC5/MOSI PA1 PA0 PC7/SS PC6/SCK EPROM/OTP only PP ST72E311 ST72T311 V 33 SS_1 D_1 (EI0) 31 PA3 30 PC7/SS 29 PC6/SCK 28 PC5/MOSI 27 PC4/MISO 26 PC3/ICAP1_B 25 PC2/ICAP2_B 24 PC1/OCMP1_B 23 PC0/OCMP2_B ...
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... ST72E311 ST72T311 Table 1. ST72T311Nx Pin Description Pin n Pin n Pin Name Type QFP64 SDIP56 1 49 PE4 I PE5 I PE6 I PE7 I PB0 I PB1 I PB2 I PB3 I PB4 I PB5 I PB6 I PB7 I PD0/AIN0 I PD1/AIN1 ...
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... OSCOUT OSCIN DD_2 61 47 PE0/TDO I PE1/RDI I Note EPROM/OTP only. PP Table 2. ST72T311Jx Pin Description Pin n Pin n Pin Name QFP44 SDIP42 1 38 PE1/RDI 2 39 PB0 3 40 PB1 4 41 PB2 5 42 PB3 6 1 PB4 7 2 PD0/AIN0 8 ...
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... ST72E311 ST72T311 Pin n Pin n Pin Name QFP44 SDIP42 19 14 PF6/ICAP1_A 20 15 PF7/EXTCLK_A 21 V DD_0 22 V SS_0 23 16 PC0/OCMP2_B 24 17 PC1/OCMP1_B 25 18 PC2/ICAP2_B 26 19 PC3/ICAP1_B 27 20 PC4/MISO 28 21 PC5/MOSI 29 22 PC6/SCK 30 23 PC7/ PA3 DD_1 SS_1 34 27 PA4 35 28 ...
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... Unused I/Os should be tied high to avoid any un- necessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up 0 See DDA A/D Converter Section V SSA V DD 4.7K 0.1 F RESET 0.1 F OSCIN See Clocks Section OSCOUT 10K V Unused I/O DD ST72E311 ST72T311 9/100 9 ...
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... ST72E311 ST72T311 1.4 MEMORY MAP Figure 7. Program Memory Map 0000h HW Registers (see Table 4) 007Fh 0080h 384 Bytes RAM 01FFh 512 Bytes RAM 027Fh 0200h / 0280h Reserved BFFFh C000h 16K Bytes Program Memoryl E000h 8K Bytes Program Memory FFDFh FFE 0h Interrupt & Reset Vectors ...
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... Data Register Data Direction Register Option Register Reserved Area (9 bytes) Miscellaneous Register SPI Data I/O Register SPI Control Register SPI Status Register Reserved Area (6 bytes) Watchdog Control Register Watchdog Status Register Reserved Area (5 bytes) ST72E311 ST72T311 Reset Remarks Status 00h R/W 00h R/W 1) 00h R/W 00h ...
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... ST72E311 ST72T311 Register Address Block Label 0031h TACR2 0032h TACR1 0033h TASR 0034h-0035h TAIC1HR TAIC1LR 0036h-0037h TAOC1HR TAOC1LR 0038h-0039h Timer A TACHR TACLR 003Ah-003Bh TAACHR TAACLR 003Ch-003Dh TAIC2HR TAIC2LR 003Eh-003Fh TAOC2HR TAOC2LR 0040h 0041h TBCR2 0042h TBCR1 0043h TBSR 0044h-0045h TBIC1HR TBIC1LR ...
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... Bit 7:4 = Not used Bit 3 = Reserved, must be cleared. Bit 2 = Reserved, must be set on ST72T311N de- vices and must be cleared on ST72T311J devices. Bit 1 = Not used Bit 0 = WDG Watchdog disable 0: The Watchdog is enabled after reset (Hardware Watchdog). 1: The Watchdog is not enabled after reset (Soft- ware Watchdog) ...
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... ST72E311 ST72T311 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers ...
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... No overflow or underflow has occurred overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions also affected by the “bit test and branch”, shift and rotate instructions. ST72E311 ST72T311 th 15/100 15 ...
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... ST72E311 ST72T311 CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01FFh SP7 SP6 SP5 SP4 SP3 SP2 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free location in the stack then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9) ...
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... Figure 10. External Clock Source Connections ) is derived ) The OSC . OSCIN EXTERNAL CLOCK . The osc Figure 11. Crystal/Ceramic Resonator OSCIN C OSCIN Figure 12. Clock Prescaler Block Diagram 150 22pF 22pF OSCIN OSCOUT C OSCIN ST72E311 ST72T311 OSCOUT NC OSCOUT C OSCOUT % CPU to CPU and Peripherals C OSCOUT 17/100 17 ...
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... ST72E311 ST72T311 3.2 RESET 3.2.1 Introduction There are four sources of Reset: – RESET pin (external source) – Power-On Reset (Internal source) – WATCHDOG (Internal Source) – Low Voltage Detection Reset (internal source) The Reset Service Routine vector is located at ad- dress FFFEh-FFFFh. 3.2.2 External Reset The RESET pin is both an input and an open-drain output with integrated pull-up resistor ...
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... Figure 14. Low Voltage Detector Reset Function LOW VOLTAGE V DD DETECTOR RESET WATCHDOG Figure 15. Low Voltage Detector Reset Signal , the LVDDOWN V LVDUP V DD RESET Note: See electrical characteristics for values of V and V LVDUP LVDDOWN Temporization (4096 CPU clock cycles) $FFFE ST72E311 ST72T311 RESET FROM RESET V LVDDOWN 19/100 19 ...
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... ST72E311 ST72T311 3.3 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 17. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled ...
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... INTERRUPTS (Cont’d) Figure 17. Interrupt Processing Flowchart FROM RESET EXECU TE INSTRUCTION N BIT I SET N Y FETCH NEXT INSTR UCTION N IRET STACK PC LOAD PC FROM INTERRUPT VECTO R RESTORE PC FROM STACK THIS CLEARS I BIT BY DEFAULT ST72E311 ST72T311 BIT I SET Y SET I BIT 21/100 21 ...
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... ST72E311 ST72T311 Table 6. Interrupt Mapping Source Description Block RESET Reset TRAP Software NOT USED NOT USED EI0 Ext. Interrupt (Ports PA0:PA3) EI1 Ext. Interrupt (Ports PF0:PF2) EI2 Ext. Interrupt (Ports PB0:PB3) EI3 Ext. Interrupt (Ports PB4:PB7) NOT USED Transfer Complete SPI ...
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... Reset occurs, whereupon the Program Counter branches to the starting address of the In- terrupt or Reset Service Routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 18 below. ST72E311 ST72T311 Figure 18. WAIT Flow Chart WFI INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK ...
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... ST72E311 ST72T311 POWER SAVING MODES (Cont’d) 3.4.4 Halt Mode The Halt mode is the MCU lowest power con- sumption mode. The Halt mode is entered by exe- cuting the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals ...
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... CPU OSC OSC OSC OSC Bit 0 = SMS Slow Mode Select This bit is set and cleared by software. 0: Normal Mode - f (Reset state) 1: Slow Mode - the f PSM[1:0] bits. ST72E311 ST72T311 PEI1 PEI0 PSM1 PSM0 ...
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... ST72E311 ST72T311 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS 4.1.1 Introduction The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – analog signal input (ADC) – alternate signal input/output for the on-chip pe- ripherals. – external interrupt generation An I/O port is composed pins ...
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... Recommended safe transitions are il- lustrated in Figure 20. Other transitions are poten- tially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. INPUT OUTPUT open-drain ST72E311 ST72T311 OUTPUT push-pull 27/100 27 ...
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... ST72E311 ST72T311 I/O PORTS (Cont’d) . Figure 21 I/O Block Diagram ALTERNATE OUTPUT DR LATCH DDR LATCH OR LATCH ( ABLE BELOW OR SEL DDR SEL DR SEL ALTERNATE INPUT POLARITY FROM SEL EXTERNAL OTHER BITS INTERRUPT SOURCE (EIx) Table 10. Port Mode Configuration Configuratio n Mode Floating Pull-up ...
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... Port F PF4, PF6, PF7 Notes: 1. ST72T311N only 2. For OTP/EPROM version, when OR=0: floating & when OR=1: reserved 3. For OTP/EPROM version, when OR=0: open-drain, high sink capability & when OR=1: reserved * Reset state (The bits corresponding to unavailable pins are forced hardware, this affects the reset status value). ...
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... ST72E311 ST72T311 I/O PORTS (Cont’d) 4.1.4 Register Description 4.1.4.1 Data registers Port A Data Register (PADR) Port B Data Register (PBDR) Port C Data Register (PCDR) Port D Data Register (PDDR) Port E Data Register (PEDR) Port F Data Register (PFDR) Read/Write Reset Value: 0000 0000 (00h ...
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... DD4 DD3 DD6 DD5 DD4 DD3 DD6 DD5 DD4 DD3 ST72E311 ST72T311 DD2 DD1 DD0 DD2 DD1 DD0 DD2 DD1 DD0 O2 O1 ...
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... ST72E311 ST72T311 4.2 WATCHDOG TIMER (WDG) 4.2.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset on expiry of a pro- grammed time period, unless the program refresh- es the counter’ ...
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... This bit is useful for distinguishing power/on off or external reset and watchdog reset Watchdog reset occurred 1: Watchdog reset occurred * Only by software and power on/off reset Note: This register is not used in versions without LVD Reset. ST72E311 ST72T311 ...
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... ST72E311 ST72T311 Table 14. WDG Register Map Address Register Label (Hex.) WDGCR WDGA 2A Reset Value WDGSR 2B Reset Value 34/100 WDOGF ...
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... Some external pins are not available on all devices. Refer to the device pin out description. When reading an input signal which is not availa- ble on an external pin, the value will always be ‘1’. ST72E311 ST72T311 4.3.3 Functional Description 4.3.3.1 Counter The principal block of the Programmable Timer is ...
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... ST72E311 ST72T311 16-BIT TIMER (Cont’d) Figure 23. Timer Block Diagram f CPU 8 low 8 high 8-bit buffer EXEDG 16 16 BIT 1/2 FREE RUNNING 1/4 COUNTER 1/8 COUNTER ALTERNATE REGISTER 16 CC1 CC0 OVERFLOW EXTCLK DETECT CIRCUIT ICF1 OCF1 TOF ICF2 OCF2 SR ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 ...
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... I bit of the CC register is cleared. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. ST72E311 ST72T311 Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set access (read or write) to the CLR register. ...
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... ST72E311 ST72T311 16-BIT TIMER (Cont’d) Figure 24. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 25. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 26 ...
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... ICIE bit is set. 7. The TOF bit can be used with interrupt in order to measure event that go beyond the timer range (FFFFh). ST72E311 ST72T311 39/100 39 ...
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... ST72E311 ST72T311 16-BIT TIMER (Cont’d) Figure 27. Input Capture Block Diagram ICAP1 pin EDGE DETECT EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 28. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive edge is rising edge ...
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... OCMP i pins even if the input capture mode is also used. 5. The value in the 16-bit OC OLV i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. ST72E311 ST72T311 CPU PRESC R register: ...
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... ST72E311 ST72T311 16-BIT TIMER (Cont’d) Figure 29. Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC1R Register OC2R Register Figure 30. Output Compare Timing Diagram, Internal Clock Divided by 2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER OUTPUT COMPARE REGISTER ...
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... Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. ST72E311 ST72T311 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set OCMP1 = OLVL1 ...
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... ST72E311 ST72T311 One Figure 32. Pulse Mode Timing Example .... FFFC FFFD FFFE COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 33. Pulse Width Modulation Mode Timing Example 34E2 FFFC FFFD FFFE COUNTER OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 44/100 44 2ED0 2ED1 2ED2 ...
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... ICF1 can also generates interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one ST72E311 ST72T311 Pulse Width Modulation cycle OCMP1 = OLVL1 OCMP1 = OLVL2 Counter is reset ...
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... ST72E311 ST72T311 16-BIT TIMER (Cont’d) 4.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken interrupt with “ ...
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... Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited timer interrupt is enabled whenever the TOF bit of the SR register is set. ST72E311 ST72T311 Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison ...
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... ST72E311 ST72T311 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Com- pare mode, both OLV1 and OLV2 in PWM and one-pulse mode) ...
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... CHR register. 7 MSB OUTPUT COMPARE (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 MSB ST72E311 ST72T311 0 LSB 0 LSB 1 HIGH REGISTER 0 LSB 1 LOW ...
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... ST72E311 ST72T311 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 LOW (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register ...
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... ST72E311 ST72T311 OLVL2 IEDG1 OLVL1 CC0 IEDG2 EXEDG LSB - - - LSB - - - - - LSB LSB LSB LSB LSB ...
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... ST72E311 ST72T311 4.4 SERIAL COMMUNICATIONS INTERFACE (SCI) 4.4.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range of baud rates using two baud rate generator systems. ...
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... M WAKE WAKE UP RECEIVE R CONTROL UNIT TE RE RWU SBK TDRE TC RDRF IDLE OR TRANS MITTER RATE CONTROL /PR SCP1 SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0 CONVEN TIONAL BAUD RATE GENERATOR ST72E311 ST72T311 (DATA REGIST ER) DR CR1 - - - RECEIVER CLOCK BRR RECEIVER RATE CONTROL 53/100 53 ...
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... ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 4.4.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 34. It contains 6 dedicated reg- isters: – Two control registers (CR1 & CR2) – A status register (SR) – A baud rate register (BRR) – An extended prescaler receiver register (ERPR) – ...
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... DR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. ST72E311 ST72T311 When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register ...
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... ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 4.4.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 reg- ister. Character reception During a SCI reception, data shifts in least signifi- cant bit first through the RDI pin ...
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... EXTE NDED RECEIVER PRESCALER REGISTER EXTE NDED PRESCALER RECEIVER RATE CONTROL f CPU /2 /PR /16 ETPR ERPR EXTENDED PRESCALER TRANSMIT TER RATE CONTROL BRR SCP1 SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0 RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR ST72E311 ST72T311 TRANSMI TTER CLOCK RECEIVER CLOCK 57/100 57 ...
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... ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 4.4.4.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows CPU (32 (32 PR with (see SCP0 & SCP1 bits 16, 32, 64,128 (see SCT0, SCT1 & ...
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... Interrupt Event Transmit Data Register Empty Transmission Complete Received Data Ready to be Read Overrrun Error Detected Idle Line Detected The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). ST72E311 ST72T311 Enable Exit Event Control from Flag Bit ...
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... ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 4.4.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR NF Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register ...
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... This bit set is used to send break characters set and cleared by software break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word. ST72E311 ST72T311 61/100 61 ...
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... ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 DR2 The Data register performs a double function (read ...
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... T8 M WAKE - - - - TCIE RIE ILIE ERPR6 ERPR5 ERPR4 ERPR3 ETPR6 ETPR5 ETPR4 ETPR3 ST72E311 ST72T311 0 ETPR ETPR ETPR ETPR ETPR DR2 DR1 DR0 - - - SCR2 SCR1 SCR0 ...
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... ST72E311 ST72T311 4.5 SERIAL PERIPHERAL INTERFACE (SPI) 4.5.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller ...
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... Figure 38. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS Internal Bus DR SPIF WCOL SPI STATE CONTROL SPIE SPE SPR2 MSTR MASTER CONTROL SERIAL CLOCK GENERATOR ST72E311 ST72T311 IT request SR MODF - - - - - CR CPOL CPHA SPR1 SPR0 65/100 65 ...
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... ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) 4.5.4 Functional Description Figure 37 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to the CR, SR and DR registers in Section 4.5.7for the bit definitions. ...
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... The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. ST72E311 ST72T311 When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared ...
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... ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) 4.5.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device ...
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... Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. CPHA =1 Bit 4 Bit3 Bit 2 Bit 5 Bit 4 Bit3 Bit 2 Bit 5 CPHA =0 Bit 4 Bit3 Bit 2 Bit 5 Bit 5 Bit 4 Bit3 Bit 2 ST72E311 ST72T311 Bit 1 LSBit Bit 1 LSBit Bit 1 LSBit Bit 1 LSBit VR02131B 69/100 69 ...
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... ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) 4.5.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. ...
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... MCUs, the SS pin must be pulled high during the clearing se- quence of the MODF bit. The SPE and MSTR bits ST72E311 ST72T311 may be restored to their original state during or af- ter this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence ...
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... ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) 4.5.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 42) ...
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... Master Mode Fault Event Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC reg- ister is reset (RIM instruction). ST72E311 ST72T311 Description Enable Event Control Flag ...
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... ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) 4.5.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register Bit 6 = SPE Serial peripheral output enable ...
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... Warning: A write to the DR register places data directly into the shift register for transmission. A write to the the DR register returns the value lo- cated in the buffer and not the contents of the shift register (See Figure 38 ). ST72E311 ST72T311 75/100 ...
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... ST72E311 ST72T311 Table 19. SPI Register Map and Reset Values Address Register 7 Name (Hex Reset Value x CR SPIE 22 Reset Value 0 SR SPIF 23 Reset Value 0 76/100 SPE SPR2 MSTR CPOL WCOL - MODF - ...
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... Conversion complete status flag On/off bit (to reduce consumption) The block diagram is shown in Figure 43. - ADON 0 COCO (Control Status Register) CSR SAMPLE ANALOG TO & DIGITAL HOLD CONVERTER AD6 AD5 AD4 AD7 ST72E311 ST72T311 - CH2 CH1 CH0 AD3 AD2 AD1 AD0 (Data Register) DR 77/100 77 ...
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... ST72E311 ST72T311 8-BIT A/D CONVERTER (ADC) (Cont’d) 4.6.3 Functional Description The high level reference voltage V connected externally to the V pin. The low level DD reference voltage V must be connected exter- SSA nally to the V pin. In some devices (refer to de- SS vice pin out description) high and low level refer- ...
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... This register contains the converted analog value in the range 00h to FFh. Reading this register reset the COCO flag AD6 AD5 AD4 AD3 ADON ST72E311 ST72T311 CH1 CH0 ...
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... ST72E311 ST72T311 5 INSTRUCTION SET 5.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction Table 22 ...
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... Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations ST72E311 ST72T311 5.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows address- ing space ...
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... ST72E311 ST72T311 ST7 ADDRESSING MODES (Cont’d) 5.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register value ( with a pointer value located in memory. The point- er address follows the opcode ...
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... It also changes an instruction using X indexed ad- dressing mode to an instruction using indirect X in- dexed addressing mode. PIY 91 Replace an instruction using X in- direct indexed addressing mode one. ST72E311 ST72T311 SWAP SLA CALLR NOP RET 83/100 83 ...
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... ST72E311 ST72T311 INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory tst ( BRES Bit Reset bres Byte, #3 BSET Bit Set bset Byte, #3 BTJF Jump if bit is false (0) ...
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... XOR M Function/Example Dst Src reg reg reg reg reg, CC reg, M reg reg, M reg, M reg, M reg ST72E311 ST72T311 ...
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... ST72E311 ST72T311 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V ...
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... OSC MHz 3.0 OSC 3. 3.5V (1 & 6 Suffix Versus Supply Voltage (V OSC 4 4.5 5 5.5 FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR ST72E311 ST72T311 Value Unit Typ. Max 125 C 5.5 V 5.5 8 MHz FUNCTIONALITY GUARANTEED IN THIS AREA Supplly Voltage [V] 6 87/100 ...
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... ST72E311 ST72T311 6.3 DC ELECTRICAL CHARACTERISTICS ( +125 C and unless otherwise specified Symbol Parameter Input Low Level Voltage V 3V < All Input pins Input High Level Voltage V 3V < All Input pins 1) Hysteresis Voltage V HYS All Input pins Low Level Output Voltage ...
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... Based on characterisation results, not tested. Condition s V > < Test Conditions Min 10% DD Conditions rising edge MHz max . OSC falling edge 2) ST72E311 ST72T311 1) Min Typ Max Unit 120 240 Value Unit Typ. Max. 9 mA/V 16 MHz ...
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... ST72E311 ST72T311 PERIPHERAL CHARACTERISTICS (Cont’ - +125 C and 10% unless otherwise specified ) A DD Symbol Parameter T Sample Duration SAMPLE Res ADC Resolution DLE Differential Linearity Error* ILE Integral Linearity Error* V Analog Input Voltage AIN Supply current rise I ADC during A/D conversion ...
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... The ideal transf er curve (3) Differe ntial no n-linearity error (DLE) (4) Integral non-lineari tyerror (ILE) (5) Center of a ste p of the actual transfer curve 7 250 251 252 253 254 255 256 V (LSB ) in(A) ideal ST72E311 ST72T311 Gain Error GE V – V ref P ref M = ------------------------ --------------- - ideal 256 VR02133A ...
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... ST72E311 ST72T311 PERIPHERAL CHARACTERISTICS (Cont’d) Ref. Symbol Parameter f SPI frequency SPI 1 t SPI clock periode SPI 2 t Enable lead time Lead 3 t Enable lag time Lag 4 t Clock (SCK) high time SPI_H 5 t Clock (SCK) low time SPI_L 6 t Data set-up time ...
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... Figure 50. SPI Master Timing Diagram CPHA=1, CPOL=1 SS (INPUT) SCK (OUTPUT) 5 MISO D7-IN (INPUT MOSI D7-OUT (OUTPUT) 10 and V in the SPI Timing Diagram D6-IN D6-OUT D7-OUT D6-OUT D6- D6-IN D6-OUT 11 ST72E311 ST72T311 D0-IN D0-OUT VR000110 D0-OUT D0-IN VR000107 D0-IN D0-OUT VR000108 93/100 ...
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... ST72E311 ST72T311 PERIPHERAL CHARACTERISTICS (Cont’d) Measurement points are Figure 51. SPI Slave Timing Diagram CPHA=0, CPOL=0 SS (INPUT) 2 SCK (INPUT) 4 MISO HIGH-Z D7-OUT (OUTPU MOSI D7-IN (INPUT Figure 52. SPI Slave Timing Diagram CPHA=0, CPOL=1 SS (INPUT) 2 SCK (INPUT) 5 MISO HIGH-Z ...
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... UV content of sunlight can be sufficient to cause functional fail- ure. Extended exposure to room level fluorescent lighting may also cause erasure. ST72E311 ST72T311 An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product operated under these lighting con- ditions ...
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... ST72E311 ST72T311 7.2 PACKAGE MECHANICAL DATA Figure 55. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width Figure 56. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width 96/100 Dim. Min A A1 0. 0.23 D 36.58 36.83 37.08 1.440 1.450 1.460 E 15.24 E1 12.70 13.72 14.48 0.500 0.540 0.570 e eA 15. PDIP42S L 2.54 N Dim. ...
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... LEADDETAIL eA VR01725H Dim 18.69 18.95 19.20 0.736 0.746 0.756 G2 G3 11.05 11.30 11.56 0.435 0.445 0.455 G4 15.11 15.37 15.62 0.595 0.605 0.615 CDIP56SW ST72E311 ST72T311 mm inches Min Typ Max Min Typ Max 6.35 0.250 0.38 0.015 3.18 4.95 0.125 0.195 0.41 0.016 0.89 0.035 0.20 0.38 0.008 0.015 50.29 53.21 1.980 2.095 15 ...
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... ST72E311 ST72T311 Figure 59. 64-Pin Thin Quad Flat Package Figure 60. 44-Pin Thin Quad Flat Package L1 98/100 0.10mm .004 Dim seating plane 0.10mm .004 Dim seating plane ...
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... Care must be taken to only use resources available on the target device. S= LVD Reset option 3 = automotive -40 to +125 C 6= industrial - Plastic DIP T= Plastic TQFP ST72T311J2 ST72T311J4 ST72T311N2 ST72T311N4 ST72E311 ST72T311 99/100 ...
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... ST72E311 ST72T311 8 SUMMARY OF CHANGES Change Description (Rev. 1.5 to 1.6) Added new External Connections section Removed RP external resistor Changed ORed to ANDed in External interrupts paragraph, to read “If several input pins, con- nected to the same interrupt vector, are configured as interrupts, their signals are logically AN- Ded before entering the edge/level detection block”. ...