AS7C256A ETC, AS7C256A Datasheet - Page 6

• Manufacturer Part Number: AS7C256A
• Description: 5V/3.3V 32K X 8 CMOS SRAM (Common I/O)
• Manufacturer: ETC

Data retention characteristics (over the operating range)
Parameter
Data retention waveform
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
V
Chip enable to data retention time t
Operation recovery time
Input leakage current
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
CC
+3.0V
3/7/01; V.0.9.2
GND
During V
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured 500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
V
for data retention
C E
CC
10%
CC
Figure A: Input pulse
90%
power-up, a pull-up resistor to V
2 ns
90%
10%
Symbol
V
t
CDR
R
I
DR
LI
V
VCC
CC
IH
on CE is required to meet I
t
CDR
Alliance Semiconductor
D
out
255
Figure B: Output load
Data retention mode
V
V
CE
Test conditions
DR
IN
SB
V
V
V
CC
IN
specification.
DR
V
V
®
2.0V
= 2.0V
CC
or
CC
+5V
480
C(14)
GND
0.2V
–0.2V
–0.2V
Figure C: Output load
D
Min
Thevenin equivalent
D
2.0
0
t
–
RC
out
out
350
VCC
V
168
IH
t
R
Max
+1.72V (5V and 3.3V)
–
–
–
1
+3.3V
320
C(14)
GND
AS7C3256A
AS7C256A
Unit
V
ns
ns
µA
P. 6 of 8