GS8160Z18 ETC, GS8160Z18 Datasheet

GS8160Z18

Manufacturer Part Number

GS8160Z18

Description

18Mb Pipelined and Flow Through Synchronous NBT SRAM

Manufacturer

ETC

Datasheet

1.GS8160Z18.pdf (26 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

Rev: 2.13a 9/2002

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Flow Through

Through

Pipeline

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

3-1-1-1

2-1-1-1

3.3 V

2.5 V

Flow

3.3 V

2.5 V

Read/Write

Pipelined

Address

Data I/O

Clock

Curr

tCycle

(x32/x36)

(x18)

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

-250 -225 -200 -166 -150 -133 Unit

280

330

275

320

175

200

175

200

2.5

4.0

5.5

18Mb Pipelined and Flow Through

255

300

250

295

165

190

165

190

2.7

4.4

6.0

230

270

230

265

160

180

160

180

3.0

5.0

6.5

Synchronous NBT SRAM

200

230

195

225

150

170

150

170

3.4

6.0

7.0

185

215

180

210

145

165

145

165

3.8

6.7

7.5

165

190

165

185

135

150

135

150

4.0

7.5

8.5

1/26

Functional Description

The GS8160Z18/36T is an 18Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8160Z18/36T may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, meaning that in addition to the rising edge

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8160Z18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 100-pin TQFP package.

GS8160Z18/36T-250/225/200/166/150/133

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS8160Z18

GS8160Z18 Summary of contents

Page 1

... SRAMs and simplifies input signal timing. 200 185 165 mA 230 215 190 mA The GS8160Z18/36T may be configured by the user to operate 195 180 165 mA in Pipeline or Flow Through mode. Operating as a pipelined 225 210 185 mA synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device 7 ...

Page 2

... GS8160Z18T Pinout 100 DDQ DDQ DDQ V 21 ...

Page 3

Page 4

... DDQ Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Description Burst Address Inputs; Preload the burst counter Address Inputs Address Input Clock Input Signal Byte Write signal for data inputs DQ ...

Page 5

... GS8160Z18/36 NBT SRAM Functional Block Diagram Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Amps Sense Drivers Write 5/26 © 1998, Giga Semiconductor, Inc. ...

Page 6

... Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 , ...

Page 7

... This device contains circuitry that ensures all outputs are in High Z during power-up 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 ADV CKE CK 1 ...

Page 8

... Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition for Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 D B Deselect ...

Page 9

... Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Intermediate R D Intermediate Intermediate W R High Z B ...

Page 10

... Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 High Notes 1. The Hold command (CKE Low) is not 2 ...

Page 11

... Note: The burst counter wraps to initial state on the 5th clock. Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Function L Linear Burst LBO H Interleaved Burst Active ...

Page 12

... Pin 14. Not all vendors offer this option, however most mark Pin through parts. GSI NBT SRAMs are fully compatible with these sockets. Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Sleep tZZS tZZH ...

Page 13

... Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Description Pins DD Pins DDQ – ...

Page 14

... Input Under/overshoot voltage must be –2 V > Vi < (max) is voltage on V pins plus 0.3 V. IHQ DDQ Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Symbol Min. Typ. V 3.0 3.3 DD3 V 2.3 2.5 ...

Page 15

... PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Symbol Min – ...

Page 16

... ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Conditions V – ...

Page 17

Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS18/36-250/225/200/166/150/133 17/26 © 1998, Giga Semiconductor, Inc. ...

Page 18

... asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 -250 -225 Min ...

Page 19

... – Write Write COMMAND D(A2) D(A1) *Note High (False Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 tKH tKL tKC A3 A4 tKQ tKQHZ tKQLZ D D(A2) Q(A3) D(A1) (A2+1) tS ...

Page 20

... ADV – Write D(A1) COMMAND *Note High (False Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Q(A2) D(A1) Read STALL Read Write Q(A2) Q(A3) D(A4) DON’T CARE = ...

Page 21

... – D(A1 Write COMMAND D(A1) *Note High (False Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 tKH tKL tKC tKQ tGLQV tKQHZ tKQLZ D D(A2) Q(A3) Q(A4) (A2+1) ...

Page 22

... ADV – Write COMMAND D(A1) *Note High (False Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Q(A2) D(A1) Q(A3) Read STALL Read Write STALL Q(A2) Q(A3) D(A4) DON’ ...

Page 23

... Foot Length 0.45 L1 Lead Length — Y Coplanarity — Lead Angle 0 Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 20.1 20.0 20.1 16 ...

Page 24

... GS8160Z36T-200 512K x 36 GS8160Z36T-166 512K x 36 GS8160Z36T-150 512K x 36 GS8160Z36T-133 GS8160Z18T-250I GS8160Z18T-225I GS8160Z18T-200I GS8160Z18T-166I GS8160Z18T-150I GS8160Z18T-133I 512K x 36 GS8160Z36T-250I 512K x 36 GS8160Z36T-225I 512K x 36 GS8160Z36T-200I 512K x 36 GS8160Z36T-166I 512K x 36 GS8160Z36T-150I 512K x 36 ...

Page 25

... Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Page;Revisions;Reason • Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master Content File Rev B • Added x72 Pinout. • Added new GSI Logo Format • ...

Page 26

... Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Page;Revisions;Reason • Updated table on page 1 • Created recommended operating conditions tables on pages 13 and 14 • Updated AC Electrical Characteristics table Content • ...

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