AM29DL640G AMD, AM29DL640G Datasheet

Page 1

... PRELIMINARY Am29DL640G 64 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another bank. — Zero latency between read and write operations ...

Page 2

... GENERAL DESCRIPTION The Am29DL640G megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt V supply, and can also be programmed in standard EPROM programmers ...

Page 3

... Table 2. Am29DL640G Sector Architecture ....................................11 Table 3. Bank Address ....................................................................14 TM Table 4. SecSi Sector Addresses ................................................14 Autoselect Mode..................................................................... 14 Table 5. Am29DL640G Autoselect Codes, (High Voltage Method) 15 Sector/Sector Block Protection and Unprotection .................. 16 Table 6. Am29DL640G Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................................16 Write Protect (WP#) ................................................................ 17 Table 7. WP#/ACC Modes ..............................................................17 Temporary Sector Unprotect ...

Page 4

... 2.7–3 OE# BYTE# Bank 1 Bank 1 Address X-Decoder Bank 2 Address Bank 2 X-Decoder Status Control X-Decoder Bank 3 Bank 3 Address X-Decoder Bank 4 Address Bank 4 Am29DL640G Am29DL640G 70 90 120 70 90 120 70 90 120 DQ15–DQ0 Mux June 7, 2002 ...

Page 5

... A19 DQ5 DQ12 A18 A20 DQ2 DQ10 DQ11 DQ0 DQ8 DQ9 CE# OE# Am29DL640G 48 A16 47 BYTE DQ15/A-1 44 DQ7 43 DQ14 42 DQ6 41 DQ13 40 DQ5 39 DQ12 38 DQ4 DQ11 35 DQ3 34 DQ10 33 DQ2 ...

Page 6

... F1 RFU RFU RFU V IO Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time. Am29DL640G G8 H8 RFU RFU G7 H7 DQ15 ...

Page 7

... CC (see Product Selector Guide for speed options and voltage supply toler- ances Device Ground Pin Not Connected Internally June 7, 2002 LOGIC SYMBOL 22 A21–A0 CE# OE# WE# WP#/ACC RESET# BYTE# Am29DL640G DQ15–DQ0 (A-1) RY/BY# 7 ...

Page 8

... WH = 63-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations Valid Combinations for BGA Packages Order Number EI Am29DL640G65 EI, EE Am29DL640G70 Am29DL640G90 Am29DL640G120 Am29DL640G F BGA), Package Marking PCI D640G65P WHI D640G65V PCI ...

Page 9

... The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the Table 1. Am29DL640G Device Bus Operations Operation CE# OE# Read ...

Page 10

... If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed the DC Characteristics table represents the CC3 standby current specification. Am29DL640G must not be asserted the DC Characteristics table CC7 ± 0 but not within ...

Page 11

... The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held Table 2. Am29DL640G Sector Architecture Sector Address Bank Sector A21–A12 SA0 0000000000 ...

Page 12

... Table 2. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA23 0010000xxx SA24 0010001xxx SA25 0010010xxx SA26 0010011xxx SA27 0010100xxx SA28 0010101xxx SA29 0010110xxx SA30 0010111xxx SA31 0011000xxx SA32 0011001xxx SA33 0011010xxx SA34 0011011xxx SA35 0011000xxx SA36 0011101xxx SA37 0011110xxx ...

Page 13

... Table 2. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA71 1000000xxx SA72 1000001xxx SA73 1000010xxx SA74 1000011xxx SA75 1000100xxx SA76 1000101xxx SA77 1000110xxx SA78 1000111xxx SA79 1001000xxx SA80 1001001xxx SA81 1001010xxx SA82 1001011xxx SA83 1001100xxx SA84 1001101xxx SA85 1001110xxx ...

Page 14

... Table 2. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA119 1110000xxx SA120 1110001xxx SA121 1110010xxx SA122 1110011xxx SA123 1110100xxx SA124 1110101xxx SA125 1110110xxx SA126 1110111xxx SA127 1111000xxx SA128 1111001xxx SA129 1111010xxx Bank 4 SA130 1111011xxx SA131 1111100xxx SA132 1111101xxx SA133 ...

Page 15

... To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method Table 5. Am29DL640G Autoselect Codes, (High Voltage Method) A21 Description CE# OE# WE# A12 Manufacturer ID AMD Read Cycle 1 Read Cycle ...

Page 16

... The hard- ware sector unprotection feature re-enables both pro- gram and erase operations in previously protected sectors. Sector protection/unprotection can be imple- mented via two methods. Table 6. Am29DL640G Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A21–A12 SA0 ...

Page 17

... Notes: 1. All protected sectors unprotected (If WP#/ACC = V sectors 0, 1, 140, and 141 will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation Am29DL640G V . During this mode, formerly protected ID is removed from the RE sectors 0, 1, 140, and ...

Page 18

... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am29DL640G START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...

Page 19

... V and power-down transitions, or from system noise. Low V Write Inhibit CC When V is less than V CC cept any write cycles. This protects data during V Am29DL640G This IH ID power- the device does not ac- LKO CC ...

Page 20

... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h Am29DL640G Description June 7, 2002 ...

Page 21

... Erase Block Region 3 Information 0020h (refer to the CFI specification or CFI publication 100) 0000h 0000h 0000h Erase Block Region 4 Information 0000h (refer to the CFI specification or CFI publication 100) 0000h Am29DL640G Description pin present) PP pin present µs N µ s (00h = not supported) ...

Page 22

... Not supported Supported Bank Organization 0004h 00 = Data at 4Ah is zero Number of Banks Bank 1 Region Information 0017h X = Number of Sectors in Bank 1 Bank 2 Region Information 0030h X = Number of Sectors in Bank 2 Bank 3 Region Information 0030h X = Number of Sectors in Bank 3 Bank 4 Region Information 0017h X = Number of Sectors in Bank 4 Am29DL640G Description June 7, 2002 ...

Page 23

... The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- Am29DL640G 23 ...

Page 24

... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. Am29DL640G any operation HH June 7, 2002 ...

Page 25

... When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading Am29DL640G 25 ...

Page 26

... Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Table 12 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation Am29DL640G START Embedded Erase algorithm in progress Yes June 7, 2002 ...

Page 27

... Table 12. Am29DL640G Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID (Note 9) 6 Byte AAA SecSi Sector Factory Word 555 4 Protect (Note 10) Byte AAA Sector/Sector Block Word 555 ...

Page 28

... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm Am29DL640G Yes No Yes Yes No ...

Page 29

... Reset Command Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm Am29DL640G No Yes Yes No Yes ...

Page 30

... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of DQ3 relative to the other status bits. Am29DL640G June 7, 2002 ...

Page 31

... The device outputs array data if the system addresses a non-busy bank. June 7, 2002 Table 13. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am29DL640G DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...

Page 32

... Operating ranges define those limits between which the functionality of the device is guaranteed +0.8 V –0.5 V –2 Figure 7. Maximum Negative Overshoot Waveform +0 +2 +0 Figure 8. Maximum Positive Overshoot Waveform Am29DL640G June 7, 2002 ...

Page 33

... 3.0 V ± 10 3 4.0 mA min I = –2.0 mA min I = –100 µ min . max Am29DL640G Min Typ Max Unit 1.0 µA 35 µA 1.0 µ 0.2 5 µA 0.2 5 µA 0.2 5 µ ...

Page 34

... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 Am29DL640G 3000 3500 4000 3 June 7, 2002 ...

Page 35

... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am29DL640G 65, 70 90, 120 Unit 1 TTL gate L 30 100 0.0–3 ...

Page 36

... Test Setup CE Read Toggle and Data# Polling Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 13. Read Operation Timings Am29DL640G Speed Options 120 Min 120 Max 120 Max 120 Max ...

Page 37

... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 14. Reset Timings Am29DL640G All Speed Options Unit 20 µs 500 ns 500 µ ...

Page 38

... Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am29DL640G Speed Options 70 90 120 Unit 120 ns Data Output (DQ7–DQ0) Address Input Data Output (DQ14–DQ0) ...

Page 39

... Min Min Min Min Min Min Min Min Min Min Min Min Min Min Byte Typ Word Typ Typ Typ Min Min Max Am29DL640G Speed Options 120 Unit 120 ...

Page 40

... WPH A0h t BUSY is the true data at the program address. OUT Figure 17. Program Operation Timings Am29DL640G Read Status Data (last two cycles WHWH1 Status D OUT VHH June 7, 2002 ...

Page 41

... These waveforms are for the word mode. Figure 19. Chip/Sector Erase Operation Timings June 7, 2002 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am29DL640G Read Status Data WHWH2 In Complete Progress ...

Page 42

... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am29DL640G Valid PA Valid PA t CPH t CP Valid Valid In In CE# Controlled Write Cycles VA Valid Data True True Valid Data June 7, 2002 High Z High Z ...

Page 43

... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 23. DQ2 vs. DQ6 Am29DL640G Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 43 ...

Page 44

... VIDR CE# WE# RY/BY# Figure 24. Temporary Sector Unprotect Timing Diagram Min Min Min Min Program or Erase Command Sequence t RSP Am29DL640G All Speed Options Unit 500 ns 250 ns 4 µs 4 µ ...

Page 45

... For sector protect For sector unprotect Figure 25. Sector/Sector Block Protect and June 7, 2002 Valid* Valid* 60h Sector Group Protect: 150 µs Sector Group Unprotect Unprotect Timing Diagram Am29DL640G Valid* Verify 40h Status 45 ...

Page 46

... See the “Erase And Programming Performance” section for more information Min Min Min Min Min Min Min Min Min Min Byte Typ Word Typ Typ Typ Am29DL640G Speed Options 120 Unit 120 ...

Page 47

... SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am29DL640G PA DQ7# D OUT 47 ...

Page 48

... V, 1,000,000 cycles. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT V IN Test Conditions Am29DL640G Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level µs overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...

Page 49

... PHYSICAL DIMENSIONS FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA package June 7, 2002 Am29DL640G Dwg rev AF; 10/99 49 ...

Page 50

... PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array ( BGA package Am29DL640G June 7, 2002 ...

Page 51

... PHYSICAL DIMENSIONS TS 048—48-Pin Standard TSOP June 7, 2002 Am29DL640G Dwg rev AA; 10/99 51 ...

Page 52

... Product names used in this publication are for identification purposes only and may be trademarks of their respective companies Ordering Information Changed package marking for Fortified BGA (ordering designator is PC). Revision A+2 (June 7, 2002) Global Added 65 ns speed option. Am29DL640G June 7, 2002 ...