AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet
AMD-K6-IIIE+550ACR
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AMD-K6-IIIE+550ACR Summary of contents
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Publication # 23543 Issue Date: September 2000 Rev: A Amendment/0 ...
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... AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, K6, 3DNow!, and combinations thereof, AMD PowerNow!, E86, and Super7 are trademarks, FusionE86 is a service mark, and AMD-K6 and RISC86 are registered trademarks of Advanced Micro Devices, Inc. ...
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... E86™ family hardware and software development questions. Frequently accessed numbers are listed below. Additional contact information is listed on the back of this manual. AMD’s WWW site lists the latest phone numbers. Technical Support Answers to technical questions are available online, through e-mail, and by telephone. ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet To order literature: Web: www.amd.com/support/literature.html U.S. and Canada: (800) 222-9323 Third-Party Support AMD FusionE86 program partners provide an array of products designed to meet SM critical time-to-market needs. Products and solutions available include chipsets, emulators, hardware and software debuggers, board-level products, and software development tools, among others. The WWW site and the E86™ ...
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... Contents Preliminary Information AMD-K6™-IIIE+ Embedded Processor Data Sheet AMD-K6™-IIIE+ Embedded Processor Features . . . . . . . . . . 3 Process Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Super7™ Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Microarchitecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . 16 Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 17 Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Branch-Prediction Logic ...
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... AMD PowerNow!™ Technology ............................................. 143 6.1 6.2 7 Bus Cycles ................................................................................. 153 7.1 7.2 7.3 7.4 vi Preliminary Information DP[7:0] (Data Parity 108 EADS# (External Address Strobe 109 EWBE# (External Write Buffer Empty 110 FERR# (Floating-Point Error) ...
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... Test and Debug ......................................................................... 251 13.1 13.2 13.3 Contents Preliminary Information AMD-K6™-IIIE+ Embedded Processor Data Sheet Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 168 Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Signals Sampled During the Falling Transition of RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 RESET Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 200 State of Processor After INIT ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 13.4 13.5 13.6 14 Clock Control ............................................................................ 277 14.1 14.2 14.3 14.4 14.5 14.6 15 Electrical Data .......................................................................... 287 15.1 15.2 15.3 15.4 15.5 16 Signal Switching Characteristics ............................................ 297 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 17 Thermal Design ...
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... AMD-K6™-IIIE+ Processor Block Diagram . . . . . . . . . . . . . . . . 13 Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AMD-K6™-IIIE+ Processor Decode Logic . . . . . . . . . . . . . . . . . 19 AMD-K6™-IIIE+ Processor Scheduler . . . . . . . . . . . . . . . . . . . . 22 Register X and Y Pipeline Functional Units . . . . . . . . . . . . . . . 24 EAX Register with 16-Bit and 8-Bit Name Components Integer Data Registers Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ...
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... Figure 39. Page Flush/Invalidate Register (PFIR Figure 40. L2 Tag or Data Location for AMD-K6™-IIIE+ Figure 41. L2 Data —EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 42. L2 Tag Information for AMD-K6™-IIIE+ Processor—EAX . . . 52 Figure 43. Enhanced Power Management Register (EPMR Figure 44. Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 45. Task State Segment (TSS Figure 46 ...
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... Figure 104. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Figure 105. Key to Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 List of Figures AMD-K6™-IIIE+ Embedded Processor Data Sheet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Processor—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Processor—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Versions of the AMD-K6™-IIIE+ Processor . . . . . . . . . . . . . . . 278 Versions of the AMD-K6™-IIIE+ Processor . . . . . . . . . . . . . . . 279 xi ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Figure 106. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Figure 107. Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . 312 Figure 108. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Figure 109. Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 313 Figure 110. TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Figure 111 ...
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... Execution Latency and Throughput of Execution Units . . . . . 23 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 General-Purpose Register Doubleword, Word, and Byte Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AMD-K6™-IIIE+ Processor Model-Specific Registers . . . . . . . 44 Extended Feature Enable Register (EFER) Definition . . . . . . 47 SYSCALL/SYSRET Target Address Register (STAR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 54 Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 System Segment and Gate Types ...
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... RESET and Configuration Signals for 100-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 RESET and Configuration Signals for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 310 Test Signal Timing at 25 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Package Thermal Specification for Low-Power AMD-K6™-IIIE+ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 23543A/0—September 2000 List of Tables ...
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... List of Tables AMD-K6™-IIIE+ Embedded Processor Data Sheet Package Thermal Specification for Standard-Power AMD-K6™-IIIE+ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Pin Differences Between the CPGA and OBGA Packages 323 CPGA Pin Designations by Functional Grouping . . . . . . . . . . 326 CPGA Pin Designations for No Connect, Reserved, Power, and Ground Pins ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet xvi Preliminary Information 23543A/0—September 2000 List of Tables ...
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... Second Printing: Revised headings in Table 59 on page 291, Table 60 on page 292, and Table 61 on September 2000 A page 292. Changed Note 2 in Table 59 on page 291 and Table 60 on page 292 to apply to 400-MHz parts only. Revision History AMD-K6™-IIIE+ Embedded Processor Data Sheet xvii ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet xviii Preliminary Information 23543A/0—September 2000 Revision History ...
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... AMD-K6-IIIE+ processor logic symbol diagram. Chapter 5, “Signal Descriptions” on page 93, lists the signals and their descriptions alphabetically and by function. Chapter 6, “AMD PowerNow!™ Technology” on page 143, describes the enhanced power management features available on the low-power versions of the AMD-K6-IIIE+ processor. Chapter 7, “Bus Cycles” on page 153, describes and illustrates the timing and relationship of bus signals during various types of bus cycles ...
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... Chapter 13, “Test and Debug” on page 251, describes the various test and debug modes that enable the functional and manufacturing testing of systems and boards that use the AMD-K6-IIIE+ processor and that allow designers to debug the instruction execution of software components. Chapter 14, “Clock Control” on page 277, describes the five modes of clock control supported by the AMD-K6-IIIE+ processor ...
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... Chapter 18, “Pin Designations” on page 323, provides top- and bottom-view connection diagrams for each package type and lists the AMD-K6-IIIE+ processor’s pin designations by functional grouping. Chapter 19, “Package Specifications” on page 333, provides diagrams showing the specifications for the 321-pin CPGA package and the 349-ball OBGA package. Chapter 20, “ ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet xxii Preliminary Information 23543A/0—September 2000 About this Data Sheet ...
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... AMD-K6™-IIIE+ Embedded Processor The following are key features of the AMD-K6™-IIIE+ processor: Member of the AMD-K6™E family of 32-bit embedded processors Brings the power, performance, and value of the AMD-K6 family to the embedded market Enables improved time-to-market by leveraging existing hardware and software ...
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... Provides an easy upgrade path for embedded applications and a bridge to legacy applications AMD PowerNow!™ technology dynamically manages power and performance Monitors application requirements for performance or power utilization Supports continuously varying operating frequency and voltage, delivering performance on demand while dissipating the lowest amount of power possible 3DNow!™ ...
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... The AMD-K6-IIIE+ with its 256-Kbyte internal L2 cache offers the highest performance available for Super7 and Socket 7 platforms. All AMD-K6E family processors in the CPGA package share the same footprint and support the Socket 7-compatible Super7 platform. The AMD-K6E family provides embedded designers with an assured growth plan and supply stability, along with product longevity ...
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... The cache design is exceptionally fast, with the backside 256-Kbyte L2 cache operating at full processor speed. For example, the internal L2 cache of an AMD-K6-IIIE+/450 processor operates at 450 MHz and provides nine times the peak bandwidth of an external L2 cache operating at 100 MHz. The maximum peak bandwidth of an external L2 cache operating at 100 MHz is 800 Mbytes/s, while an internal L2 cache operating at 450 MHz delivers a maximum peak bandwidth of 3,600 Mbytes/s per port ...
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... In addition, the AMD-K6-IIIE+ processor adds support for five new digital signal processing (DSP) instructions, developed to enhance the performance of communications applications, including soft xDSL modems, MP3 recording, and Dolby Digital and Surround Sound processing ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet AMD PowerNow!™ Technology for Enhanced Power Management AMD has added a number of new power management features to the low-power versions of the AMD-K6-IIIE+ processor. Collectively, these hardware and software features are called AMD PowerNow!™ technology. ...
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... AMD is the world’s second-leading supplier of PC processors compatible with the microprocessors, including more than 60 million Windows-compatible processors. The AMD-K6-IIIE+ processor for embedded applications is the latest member in this long line of processors. With its combination of state-of-the-art features, industry-leading performance, high-performance 3DNow! technology and multimedia engines, x86 compatibility, and low-cost infrastructure, the AMD-K6-IIIE+ processor is the superior choice for high-performance embedded systems ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 1.3 Super7™ Platform The Super7 platform is an extension to the popular Socket 7 platform. AMD and its industry partners have invested in the future of Socket 7 with the Super7 platform initiative. The goal of the initiative is to maintain the competitive vitality of the Socket 7 infrastructure through a series of enhancements, including the development of an industry-standard 100-MHz processor bus protocol ...
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... Provides an easy upgrade path for embedded applications, as well as a bridge to legacy applications By taking advantage of the low-cost, mature Socket 7 infrastructure, the Super7 platform will continue to provide superior value and leading-edge performance for embedded systems. Chapter 1 AMD-K6™-IIIE+ Embedded Processor Data Sheet AMD-K6™-IIIE+ Embedded Processor 9 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 10 Preliminary Information AMD-K6™-IIIE+ Embedded Processor 23543A/0—September 2000 Chapter 1 ...
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... Architecture refers to the instruction set and features of a processor that are visible to software programs running on the processor. The architecture determines what software the processor can run. The architecture of the AMD-K6-IIIE+ processor is the industry-standard x86 instruction set. Microarchitecture refers to the design techniques used in the processor to reach the target cost, performance, and functionality goals ...
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... Th e Enh arch AMD-K6-IIIE+ processor enables higher processor core performance and promotes straightforward extensions, such as those added in the current AMD-K6-IIIE+ processor and those planned for the future. Instead of directly executing complex x86 instructions, which have lengths bytes, the AMD-K6-IIIE+ processor executes the simpler and easier fixed-length RISC86 operations, while maintaining the instruction coding efficiencies found in x86 programs ...
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... RISC86 operations. Note: In this chapter, “clock” refers to a processor clock. The AMD-K6-IIIE+ processor categorizes x86 instructions into three types of decodes—short, long, and vector. The decoders process either two short, one long, or one vector decode at a time ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Long decodes—x86 instructions less than or equal to 11 bytes in length Vector decodes—complex x86 instructions Short and long decodes are processed completely within the decoders. Vector decodes are started by the decoders and then completed by fetched sequences from an on-chip ROM. After decoding, the RISC86 operations are delivered to the scheduler for dispatching to the executions units ...
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... Technology AMD has taken a lead role in improving the multimedia and 3D capabilities of the x86 processor family with the introduction of 3DNow! technology, which uses a packed, single-precision, floating-point data format and Single Instruction Multiple Data (SIMD) operations based on the MMX technology model ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 2.2 Cache, Instruction Prefetch, and Predecode Bits The writeback level-one (L1) cache on the AMD-K6-IIIE+ processor is organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set associativity. The level-two (L2) cache is 256 Kbytes, and is organized as a unified, four-way set-associative cache ...
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... Prefetching The AMD-K6-IIIE+ processor conditionally performs cache prefetching, which results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. From the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles ...
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... Return Address Stack Bytes Figure 3. The Instruction Buffer Instruction Decode The AMD-K6-IIIE+ processor decode logic is designed to decode multiple x86 instructions per clock (see Figure 4 on page 19). The decode logic accepts x86 instruction bytes and their predecode bits from the instruction buffer, locates the actual instr uction bo undaries, and genera tes RI SC86 operations from these x86 instructions ...
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... RISC86 Sequencer Vector Address Figure 4. AMD-K6™-IIIE+ Processor Decode Logic The AMD-K6-IIIE+ processor uses a combination of decoders to convert x86 instructions into RISC86 operations. The hardware consists of three sets of decoders—two parallel short decoders, one long decoder, and one vector decoder. Parallel Short Decoders. The two parallel short decoders translate ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet they are designed to decode up to two x86 instructions per clock. Long Decoder. The commonly-used x86 instructions that are greater than seven bytes but not more than 11 bytes long and less-commonly-used x86 instructions that are up to seven bytes long are handled by the long decoder ...
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... MMX and 3DNow! instructions can be decoded in either or both of the short decoders. 2.4 Centralized Scheduler The scheduler is the heart of the AMD-K6-IIIE+ processor (see Figure 5 on page 22). It contains the logic necessary to manage out-of-order execution, data forwarding, register renaming, simultaneous issue and retirement of multiple RISC86 operations, and speculative execution. The scheduler’ ...
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... Operation Scheduler Figure 5. AMD-K6™-IIIE+ Processor Scheduler 2.5 Execution Units The AMD-K6-IIIE+ processor contains ten parallel execution units—store, load, integer X ALU, integer Y ALU, MMX ALU (X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU, floating-point, and branch condition. Each unit is independent and capable of handling the RISC86 operations issued to it. ...
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... Integer X Multimedia (processes MMX instructions) Integer Y Branch FPU 3DNow! Chapter 2 AMD-K6™-IIIE+ Embedded Processor Data Sheet Execution Latency and Throughput of Execution Units Function LEA/PUSH, Address (Pipelined) Memory Store (Pipelined) Memory Loads (Pipelined) Integer ALU Integer Multiply Integer Shift MMX ALU ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Register X and Pipelines instructions share pipeline control with the Integer X and Integer Y units. The register X and Y functional units are attached to the issue bus for the register X execution pipeline or the issue bus for the register Y execution pipeline or both. ...
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... Branch-Prediction Logic Sophisticated branch logic that can minimize or hide the impact of changes in program flow is designed into the AMD-K6-IIIE+ processor. Branches in x86 code fit into two categories: Unconditional branches always change program flow (that is, the branches are always taken) Conditional branches may or may not divert program flow (that is, the branches are taken or not-taken) ...
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... When a prediction is incorrect, the processor backs out to the point of the mispredicted branch instruction and restores all registers. The AMD-K6-IIIE+ processor c an support seven outstanding branches. 26 Preliminary Information Internal Architecture 23543A/0— ...
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... AMD-K6-IIIE+ processor support a twelfth MSR to control the AMD PowerNow! technology functions. See “Model-Specific Registers (MSR)” on page 44 for the MSR definitions. The model number for the AMD-K6-IIIE+ processor is Model D/[3:0], where the actual stepping can be any value in the range [3:0]. 3.1 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet General-Purpose The eight 32-bit x86 general-purpose registers are used to hold Registers integer data or memory pointers used by instructions. Table 2 contains a list of the general-purpose registers and the functions for which they are used. Table 2. Register Function ...
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... Byte Integer Word Integer Doubleword Integer Quadword Integer 63 Figure 8. Integer Data Registers Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet General-Purpose Register Doubleword, Word, and Byte Names 16-Bit Name 8-Bit Name (Word) (High-order Bits) EAX AX EBX ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Segment Registers The six 16-bit segment registers are used as pointers to areas (segments) of memory. Table 4 lists the segment registers and their functions. Figure 9 shows the format for all six segment registers. Table 4. Segment Register CS DS ...
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... JMP or CALL instruction is used. Floating-Point The floating-point execution unit in the AMD-K6-IIIE+ Registers processor is designed to perform mathematical operations on non-integer numbers. This floating-point unit conforms to the IEEE 754 and 854 standards and uses several registers to meet these standards — ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet The eight floating-point registers are physically 80 bits wide and labeled FPR0–FPR7. Figure 11 shows the format of the floating-point registers. See “Floating-Point Register Data Types” on page 34 for information on allowable floating-point data types Sign Exponent Figure 11 ...
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... Figure 13. FPU Control Word Register The FPU tag word register contains information about the registers in the register stack. Figure 14 shows the format of the FPU tag word register TAG (FPR7) (FPR6) Figure 14. FPU Tag Word Register Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Bits 11–10 9– ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Floating-Point Floating-point registers use four different types of data — Register Data Types packed decimal, single-precision real, double-precision real, and extended-precision real. Figures 15 and 16 show the formats for these registers Ignore S or Zero Description Ignored on Load, Zeros on Store 78-72 Sign Bit Figure 15 ...
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... Figure 17 shows the format of these registers. For more information, see the AMD-K6 Manual, order# 20726 and the 3DNow! Technology Manual, order# 21928. 63 Figure 17. MMX™/3DNow!™ Registers Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet ® Processor Multimedia Technology mm0 mm1 mm2 mm3 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet MMX™ Technology For the MMX instructions, the MMX registers use three types of Data Types data—packed eight-byte integer, packed quadword integer, and packed dual doubleword integer. Figure 18 on page 36 shows the format of these data types. ...
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... Figure 19 shows the format of the 3DNow! data type. Packed Single Precision Floating Point Biased S Significand Exponent S = Sign Bit Figure 19. 3DNow!™ Technology Data Types Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Biased S Exponent S = Sign Bit Software Environment 0 Significand 37 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet EFLAGS Register The EFLAGS register provides for three different types of flags — system, control, and status. The system flags provide operating system controls, the control flag provides directional information for string operations, and the status flags provide information resulting from logical and arithmetic operations ...
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... Protected Virtual Interrupts VME Virtual-8086 Mode Extensions 0 Figure 21. Control Register 4 (CR4 Page Directory Base Reserved Symbol Description PCD Page Cache Disable PWT Page Writethrough Figure 22. Control Register 3 (CR3) 31 Figure 23. Control Register 2 (CR2) Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Bit ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 31 Figure 24. Control Register 1 (CR1 Reserved Symbol Description Bit AM Alignment Mask 18 WP Write Protect 16 NE Numeric Error 5 ET Extension Type 4 TS Task Switched 3 EM Emulation 2 MP Monitor Coprocessor 1 PE Protection Enabled 0 Figure 25. Control Register 0 (CR0) ...
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... Global Exact Breakpoint # 1 Enabled L1 Local Exact Breakpoint # 1 Enabled G0 Global Exact Breakpoint # 0 Enabled L0 Local Exact Breakpoint # 0 Enabled Figure 26. Debug Register DR7 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Symbol Description LEN 3 Length of Breakpoint #3 R/W 3 Type of Transaction(s) to Trap LEN 2 Length of Breakpoint #2 R/W 2 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Reserved Symbol Description BT Breakpoint Task Switch BS Breakpoint Single Step BD Breakpoint Debug Access Detected 13 B3 Breakpoint #3 Condition Detected B2 Breakpoint #2 Condition Detected B1 Breakpoint #1 Condition Detected B0 Breakpoint #0 Condition Detected Figure 27. Debug Register DR6 DR5 DR4 Figure 28. Debug Registers DR5 and DR4 ...
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... DR3 DR2 DR1 DR0 Figure 29. Debug Registers DR3, DR2, DR1, and DR0 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Breakpoint 3 32-bit Linear Address Breakpoint 2 32-bit Linear Address Breakpoint 1 32-bit Linear Address Breakpoint 0 32-bit Linear Address Software Environment ...
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... Level-2 Cache Array Register (L2AAR) Enhanced Power Management Register (EPMR) Notes: 1. The EPMR register is supported in the low-power versions only of the AMD-K6-IIIE+ processor. For more information about the MSRs, see the Embedded AMD-K6™ Processors BIOS Design Guide Application Note, order# 23913. ...
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... Machine Check The AMD-K6-IIIE+ processor does not support the generation Address Register of a machine check exception. However, the processor does (MCAR) and Machine provide a 64-bit machine check address register (MCAR), a Check Type Register 64-bit machine check type register (MCTR), and a machine (MCTR) check enable (MCE) bit in CR4 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Test Register 12 Test register 12 provides a method for disabling the L1 caches. (TR12) Figure 32 shows the format of TR12. The TR12 register is MSR 0Eh. 63 Symbol Reserved CI Figure 32. Test Register 12 (TR12) Time Stamp Counter With each processor clock cycle, the processor increments the 64-bit time stamp counter (TSC) MSR ...
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... System Call 0 R/W Extension (SCE) For more information about the EWBEC bits, see “EWBE# Control” on page 229. Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Bit 4 3 Writing any reserved bit causes a general protection fault to occur. All reserved bits are always read as 0. ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet SYSCALL/SYSRET The SYSCALL/SYSRET target address register (STAR) Target Address contains the target EIP address used by the SYSCALL Register (STAR) instruction and the 16-bit code and stack segment selector bases used by the SYSCALL and SYSRET instructions. Figure 35 shows the format of the STAR register, and Table 7 defines the function of each bit of the STAR register ...
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... Processor State The AMD-K6-IIIE+ processor provides the Processor State Observability Observability Register (PSOR). The PSOR is defined as shown Register (PSOR AMD-K6-IIIE+ processor. For a description of the PSOR register supported by the low-power versions of the processor, see page 148. The PSOR register is MSR C000_0087h Reserved ...
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... Page Fault Occurred F/I Flush/Invalidate Command Figure 39. Page Flush/Invalidate Register (PFIR) Level-2 Cache Array The AMD-K6-IIIE+ processor provides the L2AAR register that Access Register allows for direct access to the L2 cache and L2 tag arrays. The (L2AAR) L2AAR register is MSR C000_0089h. The operation that is performed on the L2 cache is a function of the instruction executed — ...
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... Selects one of four octets Dword Selects upper (1) or lower (0) dword Figure 40. L2 Tag or Data Location for AMD-K6™-IIIE+ Processor—EDX If the L2 cache data is read (as opposed to reading the tag information), the result (doubleword) is placed in EAX in the format as illustrated in Figure 41. Similarly, if the L2 cache data is written, the write data is taken from EAX ...
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... AMD PowerNow! technology features. The EPMR is MSR C000_0086h. See “AMD PowerNow!™ Technology” on page 143 for more information about the definition and use of this register. Additional information can be found in the Embedded AMD-K6™ ...
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... Reserved Symbol Description IOBASE I/O Base Address GSBC Generate Special Bus Cycle EN Enable AMD PowerNow! Technology Management Figure 43. Enhanced Power Management Register (EPMR) Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet 16 15 IOBASE Bit 15 Software Environment ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 3.3 Memory Management Registers The AMD-K6-IIIE+ processor controls segmented memory management with the registers listed in Table 8. Figure 44 shows the formats of these registers. Table 8. Memory Management Registers Register Name Global Descriptor Table Register Interrupt Descriptor Table Register ...
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... Figure 45 shows the format of the task state segment (TSS). 31 Base Address of IOPB 0000h 0000h 0000h 0000h Figure 45. Task State Segment (TSS) Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet I/O Permission Bitmap (IOPB) ( Kbytes) Interrupt Redirection Bitmap (IRB) (eight 32-bit locations) Operating System Data Structure 0000h 0000h ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 3.4 Paging The AMD-K6-IIIE+ processor can physically address up to four Gbytes of memory. This memory can be segmented into pages. The size of these pages is determined by the operating system design and the values set up in the page directory entries (PDE) and page table entries (PTE) ...
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... Offset Figure 47. 4-Mbyte Paging Mechanism Figures 48 through 50 starting on page 58 show the formats of the PDE and PTE. These entries contain information regarding the location of pages and their status. Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet 4-Mbyte Physical Address 22 21 Linear Address ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 31 Page Table Base Address Symbol Description AVL Available to Software Reserved PS Page Size Reserved A Accessed PCD Page Cache Disable PWT Page Writethrough U/S User/Supervisor W/R Write/Read P Present (valid) Figure 48. Page Directory Entry 4-Kbyte Page Table (PDE) ...
Page 81
... Table 10 on page 61 contains information describing the type of segment or gate to which the descriptor points. The AMD-K6-IIIE+ processor uses gates to transfer control between executable segments with different privilege levels. Figure 53 on page 62 shows the format of the gate descriptor types ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Reserved Base Address 31– Base Address 15–0 Figure 51. Application Segment Descriptor Table 9. Type Data/Code Description Preliminary Information Segment P DPL 1 V Limit L Segment Limit 15–0 Application Segment Types Read-Only Read-Only—Accessed Read/Write Read/Write—Accessed Data Read-Only— ...
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... Base Address 31– Base Address 15–0 Figure 52. System Segment Descriptor Table 10. System Segment and Gate Types Type Description Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Segment P DPL 0 V Limit L Reserved Available 16-bit TSS LDT Busy 16-bit TSS 16-bit Call Gate ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Reserved Offset 31–16 Segment Selector Figure 53. Gate Descriptor 3.6 Exceptions and Interrupts Table 11 summarizes the exceptions and interrupts. Table 11. Summary of Exceptions and Interrupts Interrupt Interrupt Type Number 0 Divide by Zero Error 1 Debug 2 Non-Maskable Interrupt 3 Breakpoint ...
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... Instructions Supported by the AMD-K6™-IIIE+ Processor This section documents all of the x86 instructions supported by the AMD-K6-IIIE+ processor. Tables 12 through 16 starting on page 65 define the integer, floating-point, MMX, 3DNow! technology instructions, and 3DNow! technology digital signal processing (DSP) extensions for the AMD-K6-IIIE+ processor, respectively ...
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... Decode Type The fifth column lists the type of instruction decode — short, long, and vector. The AMD-K6-IIIE+ processor decode logic can process two short, one long, or one vector decode per clock. RISC86® Operation The sixth column lists the type of RISC86 operation(s) required for the instruction ...
Page 87
... ADD reg16/32, mem16/32 ADD AL, imm8 ADD EAX, imm16/32 ADD mreg8, imm8 ADD mem8, imm8 ADD mreg16/32, imm16/32 ADD mem16/32, imm16/32 ADD mreg16/32, imm8 (signed ext.) Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte 37h ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic ADD mem16/32, imm8 (signed ext.) AND mreg8, reg8 AND mem8, reg8 AND mreg16/32, reg16/32 AND mem16/32, reg16/32 AND reg8, mreg8 AND reg8, mem8 AND reg16/32, mreg16/32 AND reg16/32, mem16/32 ...
Page 89
... CMP mreg16/32, reg16/32 CMP mem16/32, reg16/32 CMP reg8, mreg8 CMP reg8, mem8 CMP reg16/32, mreg16/32 CMP reg16/32, mem16/32 CMP AL, imm8 CMP EAX, imm16/32 CMP mreg8, imm8 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte 0Fh BAh ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic CMP mem8, imm8 CMP mreg16/32, imm16/32 CMP mem16/32, imm16/32 CMP mreg16/32, imm8 (signed ext.) CMP mem16/32, imm8 (signed ext.) CMPSB mem8, mem8 CMPSW mem16, mem32 CMPSD mem32, mem32 ...
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... INC EDX INC EBX INC ESP INC EBP INC ESI INC EDI INC mreg8 INC mem8 INC mreg16/32 INC mem16/32 INVD INVLPG Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte F6h mm-111-xxx F7h 11-111-xxx F7h ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic JO short disp8 JB/JNAE short disp8 JNO short disp8 JNB/JAE short disp8 JZ/JE short disp8 JNZ/JNE short disp8 JBE/JNA short disp8 JNBE/JA short disp8 JS short disp8 JNS short disp8 ...
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... LSL reg16/32, mreg16/32 LSL reg16/32, mem16/32 LSS reg16/32, mem32/48 LTR mreg16 LTR mem16 MOV mreg8, reg8 MOV mem8, reg8 MOV mreg16/32, reg16/32 MOV mem16/32, reg16/32 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte EBh EFh ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic MOV reg8, mreg8 MOV reg8, mem8 MOV reg16/32, mreg16/32 MOV reg16/32, mem16/32 MOV mreg16, segment reg MOV mem16, segment reg MOV segment reg, mreg16 MOV segment reg, mem16 ...
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... NOP (XCHG EAX, EAX) NOT mreg8 NOT mem8 NOT mreg16/32 NOT mem16/32 OR mreg8, reg8 OR mem8, reg8 OR mreg16/32, reg16/32 OR mem16/32, reg16/32 OR reg8, mreg8 OR reg8, mem8 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte 0Fh 20h 11-100-xxx 0Fh ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic OR reg16/32, mreg16/32 OR reg16/32, mem16/32 OR AL, imm8 OR EAX, imm16/32 OR mreg8, imm8 OR mem8, imm8 OR mreg16/32, imm16/32 OR mem16/32, imm16/32 OR mreg16/32, imm8 (signed ext.) OR mem16/32, imm8 (signed ext.) OUT imm8, AL OUT imm8, AX ...
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... RCL mem16/32, 1 RCL mreg8, CL RCL mem8, CL RCL mreg16/32, CL RCL mem16/32, CL RCR mreg8, imm8 RCR mem8, imm8 RCR mreg16/32, imm8 RCR mem16/32, imm8 RCR mreg8, 1 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte 0Fh A0h 0Fh ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic RCR mem8, 1 RCR mreg16/32, 1 RCR mem16/32, 1 RCR mreg8, CL RCR mem8, CL RCR mreg16/32, CL RCR mem16/32, CL RDMSR RDTSC RET near imm16 RET near RET far imm16 RET far ROL mreg8, imm8 ...
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... SBB mem8, imm8 SBB mreg16/32, imm16/32 SBB mem16/32, imm16/32 SBB mreg16/32, imm8 (signed ext.) SBB mem16/32, imm8 (signed ext.) SCASB AL, mem8 SCASW AX, mem16 SCASD EAX, mem32 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte D3h ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic SETO mreg8 SETO mem8 SETNO mreg8 SETNO mem8 SETB/SETNAE mreg8 SETB/SETNAE mem8 SETNB/SETAE mreg8 SETNB/SETAE mem8 SETZ/SETE mreg8 SETZ/SETE mem8 SETNZ/SETNE mreg8 SETNZ/SETNE mem8 SETBE/SETNA mreg8 SETBE/SETNA mem8 ...
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... SHLD mem16/32, reg16/32, CL SHRD mreg16/32, reg16/32, imm8 SHRD mem16/32, reg16/32, imm8 SHRD mreg16/32, reg16/32, CL SHRD mem16/32, reg16/32, CL SLDT mreg16 SLDT mem16 SMSW mreg16 SMSW mem16 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte C0h mm-100-xxx ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic STC STD STI STOSB mem8, AL STOSW mem16, AX STOSD mem32, EAX STR mreg16 STR mem16 SUB mreg8, reg8 SUB mem8, reg8 SUB mreg16/32, reg16/32 SUB mem16/32, reg16/32 SUB reg8, mreg8 ...
Page 103
... XOR mem8, reg8 XOR mreg16/32, reg16/32 XOR mem16/32, reg16/32 XOR reg8, mreg8 XOR reg8, mem8 XOR reg16/32, mreg16/32 XOR reg16/32, mem16/32 XOR AL, imm8 XOR EAX, imm16/32 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte F7h mm-000-xxx ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic XOR mreg8, imm8 XOR mem8, imm8 XOR mreg16/32, imm16/32 XOR mem16/32, imm16/32 XOR mreg16/32, imm8 (signed ext.) XOR mem16/32, imm8 (signed ext.) Table 13. Floating-Point Instructions Instruction Mnemonic F2XM1 ...
Page 105
... FILD mem32int FILD mem64int FIMUL ST(0), mem32int FIMUL ST(0), mem16int FINCSTP FINIT FIST mem16int FIST mem32int FISTP mem16int FISTP mem32int FISTP mem64int Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte DCh 11-111-xxx DCh 11-111-xxx ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 13. Floating-Point Instructions (continued) Instruction Mnemonic FISUB ST(0), mem32int FISUB ST(0), mem16int FISUBR ST(0), mem32int FISUBR ST(0), mem16int 1 FLD ST(i) FLD mem32real FLD mem64real FLD mem80real FLD1 FLDCW FLDENV FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI ...
Page 107
... FUCOM FUCOMP FUCOMPP FXAM FXCH FXTRACT FYL2X FYL2XP1 FWAIT Notes: 1. The last three bits of the modR/M byte select the stack entry ST(i). Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet First Second ModR/M Decode Byte Byte Byte D9h FAh D9h mm-010-xxx ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 14. MMX™ Instructions Instruction Mnemonic EMMS 1 MOVD mmreg, mreg32 MOVD mmreg, mem32 1 MOVD mreg32, mmreg MOVD mem32, mmreg MOVQ mmreg1, mmreg2 MOVQ mmreg, mem64 MOVQ mmreg2, mmreg1 MOVQ mem64, mmreg PACKSSDW mmreg1, mmreg2 ...
Page 109
... PSLLW mmreg, imm8 PSRAD mmreg1, mmreg2 PSRAD mmreg, mem64 PSRAD mmreg, imm8 PSRAW mmreg1, mmreg2 PSRAW mmreg, mem64 PSRAW mmreg, imm8 PSRLD mmreg1, mmreg2 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Prefix First ModR/M Byte(s) Byte Byte 0Fh 74h mm-xxx-xxx ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Table 14. MMX™ Instructions (continued) Instruction Mnemonic PSRLD mmreg, mem64 PSRLD mmreg, imm8 PSRLQ mmreg1, mmreg2 PSRLQ mmreg, mem64 PSRLQ mmreg, imm8 PSRLW mmreg1, mmreg2 PSRLW mmreg, mem64 PSRLW mmreg, imm8 PSUBB mmreg1, mmreg2 ...
Page 111
... PFMUL mmreg, mem64 PFRCP mmreg1, mmreg2 PFRCP mmreg, mem64 PFRCPIT1 mmreg1, mmreg2 PFRCPIT1 mmreg, mem64 PFRCPIT2 mmreg1, mmreg2 PFRCPIT2 mmreg, mem64 PFRSQIT1 mmreg1, mmreg2 Chapter 3 AMD-K6™-IIIE+ Embedded Processor Data Sheet Prefix First ModR/M Byte(s) Byte Byte 0Fh EFh mm-xxx-xxx ...
Page 112
... Notes: 1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched. 2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-IIIE+ processor, this instruction performs in the same manner as the PREFETCH instruction. Table 16. 3DNow!™ Technology DSP Extensions ...
Page 113
... Signals with pound signs (#) are active Low. 2. The VID[4:0] outputs are supported on low-power versions only. The VCC2DET and VCC2H/L# outputs are supported on the CPGA package only. Chapter 4 AMD-K6™-IIIE+ Embedded Processor Data Sheet Clock Voltage Detection VCC2DET VCC2H/L# ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 92 Preliminary Information Logic Symbol Diagram 23543A/0—September 2000 Chapter 4 ...
Page 115
... Signal Descriptions This chapter includes a detailed description of each signal supported on the AMD-K6-IIIE+ processor. This chapter also provides tables listing the signals grouped by type, beginning on page 140. The logic symbol diagram on page 91 shows the signals grouped by function. Connection diagrams and pins listed by high-level function are included in Chapter 18, “ ...
Page 116
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.2 A20M# (Address Bit 20 Mask) Pin Attribute Input Summary A20M# is used to simulate the behavior of the 8086 when running in Real mode. The assertion of A20M # causes the processor to force bit 20 of the physical address to 0 prior to accessing the caches or driving out a memory bus cycle ...
Page 117
... HLDA in recognition of HOLD. The processor resumes driving A[31:3] off the clock edge on which the processor samples AHOLD or BOFF# negated and off the clock edge on which the processor negates HLDA. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 95 ...
Page 118
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.4 ADS# (Address Strobe) Pin Attribute Output Summary The assertion of ADS # indicates the beginning of a new bus cycle. The address bus and all cycle definition signals corresponding to this bus cycle are driven valid off the same clock edge as ADS# ...
Page 119
... If AHOLD is sampled asserted, ADS# is only asserted in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. Sampled The processor samples AHOLD on every clock edge. AHOLD is recognized while INIT and RESET are sampled asserted. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 97 ...
Page 120
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.7 AP (Address Parity) Pin Attribute Bidirectional Summary AP contains the even parity bit for cache line addresses driven and sampled on A[31:5]. Even parity means that the total number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not used for the generation or checking of address parity because these bits are not required to address a cache line ...
Page 121
... APCHK# is driven valid off the clock edge after the clock edge on which the processor samples EADS# asserted negated off the next clock edge. APCHK# is always driven except in the Three-State Test mode. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 99 ...
Page 122
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.9 BE[7:0]# (Byte Enables) Pin Attribute Output Summary BE[7:0]# are used by the processor to indicate the valid data bytes during a write cycle and the requested data bytes during a read cycle. The byte enables can be used to derive address bits A[2:0], which are not physically part of the processor’ ...
Page 123
... Sampled BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Processor-Clock to Bus-Clock Ratio 100b 101b 110b 111b ...
Page 124
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.11 BOFF# (Backoff) Pin Attribute Input Summary If BOFF # is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state by floating the following signals: A[31:3], ADS #, ADSC #, AP, BE[7:0]#, CACHE #, D[63:0], D/C #, DP[7:0], LOCK #, M/IO #, PCD, PWT, SCYC, and W/R# ...
Page 125
... Four times for a burst cycle (once for each data transfer) BRDY # can be held asserted for four consecutive clocks throughout the four transfers of the burst can be negated to insert wait states. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 103 ...
Page 126
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.13 BRDYC# (Burst Ready Copy) Pin Attribute Input, Internal Pullup Summary BRDYC # has the identical function as BRDY #. In the event BRDY # becomes too heavily loaded due to a large fanout or loading in a system, BRDYC # can be used to reduce this loading, which improves timing ...
Page 127
... The CLK signal must be stable a minimum of 1.0 ms prior to the negation of RESET to ensure the proper operation of the processor. See “CLK Switching Characteristics” on page 298 for details regarding the CLK specifications. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 105 ...
Page 128
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.17 D/C# (Data/Code) Pin Attribute Output Summary The processor drives D/C # during a memory bus cycle to indicate whether it is addressing data or executable code. D/C# is also used to define other bus cycles, including interrupt acknowledge and special cycles. See Table 23 and Table 24 on page 142 for more details ...
Page 129
... In addition, D[63:0] are floated off the clock edge that BOFF # is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 107 ...
Page 130
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.19 DP[7:0] (Data Parity) Pin Attribute Bidirectional Summary DP[7:0] are even parity bits for each valid byte of data — as defined by BE[7:0]#—driven and sampled on the D[63:0] data bus. Even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is an even number ...
Page 131
... One clock edge after the clock edge on which EADS# is sampled asserted Two clock edges after the clock edge on which ADS# is asserted When the processor is driving the address bus When the processor asserts HITM# Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 109 ...
Page 132
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.21 EWBE# (External Write Buffer Empty) Pin Attribute Input Summary The system logic can negate EWBE# to the processor to indicate that its external write buffers are full and that additional data cannot be stored at this time. This causes the processor to delay ...
Page 133
... Following the falling transition of RESET FERR# is always driven except in the Three-State Test mode. See “IGNNE# (Ignore Numeric Exception)” on page 116 for more details on floating-point exceptions. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions instructions FLDCW, 111 ...
Page 134
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.23 FLUSH# (Cache Flush) Pin Attribute Input Summary In response to sampling FLUSH# asserted, the processor writes back any cache lines in the L1 data cache or L2 cache that are in the modified state, invalidates all lines in the L1 and L2 caches, and then executes a flush acknowledge special cycle ...
Page 135
... If HITM# is asserted in response to the inquire address, it remains asserted throughout the writeback cycle and is negated one clock edge after the last BRDY # of the writeback is sampled asserted. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 113 ...
Page 136
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.26 HLDA (Hold Acknowledge) Pin Attribute Output Summary When HOLD is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts HLDA in an acknowledgment that these events have been completed. ...
Page 137
... HLDA is asserted one clock edge after the last BRDY # of the cycle is sampled asserted. If the bus is idle, HLDA is asserted one clock edge after HOLD is sampled asserted. HOLD is recognized while INIT and RESET are sampled asserted. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 115 ...
Page 138
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.28 IGNNE# (Ignore Numeric Exception) Pin Attribute Input Summary IGNNE#, in conjunction with the numeric error (NE) bit in the CR0 register, is used by the system logic to control the effect rev - MMX instruction, or the WAIT instruction—hereafter referred to as the target instruction ...
Page 139
... If INIT is asserted synchronously (see Table 19 on page 140), it can be asserted for a minimum of one clock asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 117 ...
Page 140
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.30 INTR (Maskable Interrupt) Pin Attribute Input Summary INTR is the system’s maskable interrupt input to the processor. When the processor samples and recognizes INTR asserted, the processor executes a pair of interrupt acknowledge bus cycles and then jumps to the interrupt service routine specified by the interrupt number that was returned during the interrupt acknowledge sequence ...
Page 141
... KEN# is sampled on the clock edge on which the first BRDY read cycle is sampled asserted. If the read cycle is a burst, KEN # is ignored during the last three assertions of BRDY #. KEN # is sampled during read cycles only when CACHE# is asserted. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 119 ...
Page 142
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.33 LOCK# (Bus Lock) Pin Attribute Output Summary The processor asserts LOCK# during a sequence of bus cycles to ensure that the cycles are completed without allowing other bus masters to intervene. Locked operations consist of two to five bus cycles. LOCK# is asserted during the following operations: ...
Page 143
... I/O cycles, special bus cycles, and interrupt acknowledge cycles. M/IO# is floated off the clock edge on which BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 121 ...
Page 144
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.35 NA# (Next Address) Pin Attribute Input Summary System logic asserts NA# to indicate to the processor that it is ready to accept another bus cycle pipelined into the previous bus cycle. ADS#, along with address and status signals, can be asserted as early as one clock edge after NA# is sampled asserted if the processor is prepared to start a new cycle ...
Page 145
... If NMI is asserted synchronously (see Table 19 on page 140), it can be asserted for a minimum of one clock. If NMI is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 123 ...
Page 146
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.37 PCD (Page Cache Disable) Pin Attribute Output Summary The processor drives PCD to indicate the operating system’s specification of cacheability for the page being addressed. System logic can use PCD to control external caching. If PCD is asserted, the addressed page is not cached ...
Page 147
... PCHK# is always driven except in the Three-State Test mode. For each BRDY# returned to the processor during a read cycle with a parity error detected on the data bus, PCHK# is asserted for one clock, one clock edge after BRDY# is sampled asserted. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 125 ...
Page 148
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.39 PWT (Page Writethrough) Pin Attribute Output Summary The processor drives PWT to indicate the operating system’s specification of the writeback state or writethrough state for the page being addressed. PWT, together with WB/WT#, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. See “ ...
Page 149
... CLK and V reach specification before it is negated. During a warm reset, while CLK and V specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions CC are within their CC 127 ...
Page 150
... As pins connected to the system logic as defined by the industry-standard Super7 and Socket 7 interface Any combination of NC and Socket 7 pins In any case, if the RSVD pins are treated accordingly, the normal operation of the AMD-K6-IIIE+ processor is not adversely affected in any manner. 128 Preliminary Information Signal Descriptions 23543A/0— ...
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... SCYC is only valid during locked memory cycles. SCYC is floated off the clock edge on which BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 129 ...
Page 152
... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.43 SMI# (System Management Interrupt) Pin Attribute Input, Internal Pullup Summary The assertion of SMI# causes the processor to enter System Management Mode (SMM). Upon recognizing SMI#, the processor performs the following actions, in the order shown: 1 ...
Page 153
... SMIACT# remains asserted until after the last BRDY# of the last pending bus cycle associated with exiting SMM is sampled asserted. SMIACT# remains asserted during any flush, internal snoop, or writeback cycle due to an inquire cycle. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 131 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.45 STPCLK# (Stop Clock) Pin Attribute Input, Internal Pullup Summary The assertion of STPCLK# causes the processor to enter the Stop Grant state, during which the processor’s internal clock is stopped. From the Stop Grant state, the processor can subsequently transition to the Stop Clock state, in which the bus clock CLK is stopped ...
Page 155
... TAP controller. Driven and Floated The processor drives TDO on every falling TCK edge, but only while in the Shift-IR and Shift-DR states. TDO is floated at all other times. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 133 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.49 TMS (Test Mode Select) Pin Attribute Input, Internal Pullup Summary TMS specifies the test function and sequence of state changes for boundary-scan testing using the Test Access Port (TAP). See “Boundary-Scan Test Access Port (TAP)” on page 253 for details regarding the operation of the TAP controller ...
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... Note that this pin is not supported on the OBGA package. Driven VCC2DET always equals 0 and is never floated—even during the Three-State Test mode. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet (logic level 0) to indicate to SS and V pins. The V CC2 ...
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... AMD-K6 processors to indicate core voltages of 2.9 V and 3.2 V. VCC2H/L# is driven Low for all AMD-K6 processors with a core voltage requirement of 2 less. Note that all AMD products based on the 0.18-micron process technology, including the AMD-K6-IIIE+ processor, are 2 less. Note that this pin is not supported on the OBGA package. ...
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... VID[4:0] outputs default to 01010b when RESET is sampled asserted. Note that these pins are supported on the low-power versions only of the AMD-K6-III+ processor. For more information about these signals, see the Embedded AMD-K6™ Processors BIOS Design Guide Application Note, order# 23913. ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.54 W/R# (Write/Read) Pin Attribute Output Summary The processor drives W/R# to indicate whether it is performing a write or a read cycle on the bus. In addition, W/R# is used to define other bus cycles, including interrupt acknowledge and special cycles. See Table 23 and Table 24 on page 142 for more details ...
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... NA bus cycle is sampled asserted. If the cycle is a burst read, WB/WT# is ignored during the last three assertions of BRDY #. sampled during mem ory re ad and non-writeback write cycles and is ignored during all other types of cycles. Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet Signal Descriptions 139 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.56 Pin Tables by Type Table 19. Input Pin Types Name Type 1 Asynchronous A20M# AHOLD Synchronous 3 Synchronous BF[2:0] BOFF# Synchronous BRDY# Synchronous BRDYC# Synchronous CLK Clock EADS# Synchronous 6 Synchronous EWBE# 2,7 Asynchronous FLUSH# HOLD Synchronous Notes: 1 ...
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... TDI Input Sampled on the rising edge of TCK TDO Output Driven on the falling edge of TCK TMS Input Sampled on the rising edge of TCK TRST# Input Asynchronous (Independent of TCK) Chapter 5 AMD-K6™-IIIE+ Embedded Processor Data Sheet 1 Name 2 LOCK# 2 M/IO# 2 PCD PCHK# 2 PWT 2 SCYC ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 5.57 Bus Cycle Definitions Table 23. Bus Cycle Definition Bus Cycle Initiated Code Read, L1 Instruction Cache and L2 Cache Line Fill Code Read, Noncacheable Code Read, Noncacheable Encoding for Special Cycle Interrupt Acknowledge I/O Read I/O Write ...
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... AMD PowerNow! technology can be used in conjunction with the existing power management schemes in an embedded system to provide a better combination of performance and power savings than previously possible. ...
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... Voltage ID Output bits which default to 01010b). BIOS must always initialize the EPMR register and enhanced power management features whenever RESET is asserted. For more information about the EPMR register, see the Embedded AMD-K6™ Processors BIOS Design Guide Application Note, order# 23913. 63 Reserved Symbol ...
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... EPM 16-byte I/O block. If set EPM special bus cycle is generated, where BE[7:0]# = BFh and A[4:3] = 00b. This bit controls access to the I/O-mapped address space for the AMD R/W PowerNow! EPM features. Clearing this bit to zero does not affect the state of bits defined in the EPM 16-byte I/O block. AMD PowerNow!™ ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet EPM 16-Byte I/O The EPM 16-byte I/O block contains one 4-byte field—Bus Block D iv iso Vol rol ( — for e n abl in g, controlling, and monitoring the enhanced power management features (see Figure 55). Table 26 defines the function of the BVC field within the EPM 16-byte I/O block mapped by the EPMR ...
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... Bus Divisor Control (BDC) 7-5 Internal BF Divisor (IBF[2:0]) 4-0 Voltage ID Output (VIDO) Notes: 1. All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b. Chapter 6 AMD-K6™-IIIE+ Embedded Processor Data Sheet SGTC Bits 31- 9-8 7-5 4-0 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Processor State To support AMD PowerNow! technology, all low-power versions Observability of the AMD-K6-IIIE+ processor provide a different version of Register (PSOR) the Processor State Observability Register (PSOR), as shown in Figure 57 and fully described in this section. All standard- power versions of the processor support the PSOR register as defined on page 49 ...
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... EBF field (see Table 28). The result is the frequency of the processor bus. Table 28. Processor-to-Bus Clock Ratios Notes: 1. The AMD-K6-IIIE+ processor does not support the 2.5x ratio supported by earlier AMD-K6 proces- sors. Instead, a ratio of 2.0x is selected when EBF[2:0] equals 100b. Chapter 6 AMD-K6™-IIIE+ Embedded Processor Data Sheet ...
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... Voltage ID Output (VIDO) and Internal BF Divisor (IBF) fields of the BVC field. Once the timer of the SGTC has expired, the EPM Stop Grant State is exited and the AMD PowerNow! technology state transition is completed. See “Clock Control” on page 277 for more information about the EPM Stop Grant State ...
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... Dynamic Core For AMD PowerNow! technology core frequency transitions, Frequency Control the BVC field of the EPM 16-byte I/O block is accessed through an SMM handler. To change the processor core frequency, the SMM handler initiates core voltage and frequency transitions by writing a non-zero value to the SGTC field ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 152 Preliminary Information AMD PowerNow!™ Technology 23543A/0—September 2000 Chapter 6 ...
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... ADS#, but addresses are also driven on the bus at other times.) Figure 58 on page 154 defines the different waveform representations. Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Bus Cycles 153 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Active High Signals For all active High signals, the term asserted means the signal is in the High-voltage state and the term negated means the signal is in the Low-voltage state. Active Low Signals For all active Low signals, the term asserted means the signal is in the Low-voltage state and the term negated means the signal is in the High-voltage state ...
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... Idle Idle Yes NA# Sampled Asserted? No Note: The processor transitions to the IDLE state on the clock edge on which BOFF# or RESET is sampled asserted. Figure 59. Bus State Machine Diagram Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Addr Address Data Data Yes No Last BRDY# Asserted? ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Idle The processor does not drive the system bus in the Idle state and remains in this state until a new bus cycle is requested. The processor enters this state off the clock edge on which the last BRDY cycle is sampled asserted during the following ...
Page 179
... The processor enters this state for one clock during data bus transitions and enters the Data state on the next clock edge if NA# is not sampled asserted. The sole purpose of this state is to avoid bus contention caused by bus transitions during pipeline operation. Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Bus Cycles 157 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 7.3 Memory Reads and Writes The AMD-K6-IIIE+ processor performs single or burst-memory bus cycles. The single-transfer memory bus cycle transfers bytes and requires a minimum of two clocks. Misaligned instructions or operands result in a split cycle, which requires multiple transactions on the bus. ...
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... D[63:0] DP[7:0] CACHE# EWBE# KEN# BRDY# WB/WT# Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE# Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Write Cycle (Next Cycle Delayed by EWBE#) Write Cycle DATA DATA IDLE ADDR DATA DATA Bus Cycles IDLE ...
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... ADS# and BRDY# — required to complete the access. The AMD-K6-IIIE+ processor performs misaligned memory reads and memory writes using least-significant bytes (LSBs) first followed by most-significant bytes (MSBs). Table 29 shows the order ...
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... A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# LSB D[63:0] BRDY# Figure 61. Misaligned Single-Transfer Memory Read and Write Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Memory Write (Misaligned) DATA DATA IDLE MSB LSB Bus Cycles ADDR DATA DATA DATA IDLE MSB 161 ...
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... Burst Reads and Figure 62 on page 163 shows normal burst read cycles and a Pipelined Burst Reads pipelined burst read cycle. The AMD-K6-IIIE+ processor drives CACHE# and ADS# together to specify that the current bus cycle is a burst cycle. If the processor samples KEN# asserted with the first BRDY#, it performs burst transfers ...
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... D/C# W/R# NA# DATA1 D[63:0] CACHE# KEN# BRDY# Figure 62. Burst Reads and Pipelined Burst Reads Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Burst Read DATA PIPE DATA IDLE ADDR DATA DATA -NA -ADDR ADDR2 DATA2 Bus Cycles Pipelined Burst Read DATA DATA DATA DATA IDLE ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet Burst Writeback Figure 63 on page 165 shows a burst read followed by a writeback transaction. The AMD-K6-IIIE+ processor initiates writebacks under the following conditions: Replacement—If a cache-line fill is initiated for a cache line currently filled with valid entries, the processor selects a ...
Page 187
... A[31:3] BE[7:0]# ADS# CACHE# M/IO# D/C# W/R# D[63:0] KEN# BRDY# WB/WT# Figure 63. Burst Writeback due to Cache-Line Replacement Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Burst Writeback from L1 Cache DATA ADDR DATA DATA IDLE Bus Cycles DATA DATA DATA IDLE 165 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet 7.4 I/O Read and Write Basic I/O Read and The processor accesses I/O when it executes an I/O instruction Write (for example OUT). Figure 64 shows an I/O read followed by an I/O write. The processor drives M/IO# Low and D/C# High during I/O cycles ...
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... Misaligned I/O Read Table 31 shows the misaligned I/O read and write cycle order and Write executed by the AMD-K6-IIIE+ processor. In Figure 65, the least-significant bytes (LSBs) are transferred first. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to transfer the most-significant bytes (MSBs) to complete the misaligned bus cycle ...
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... The system logic or another bus device can assert HOLD to Acknowledge Cycle initiate an inquire cycle or to gain full control of the bus. When the AMD-K6-IIIE+ processor samples HOLD asserted, it completes any in-progress bus cycle and asserts HLDA to acknowledge release of the bus. The processor floats the ...
Page 191
... The processor regains control of the bus and can assert ADS# off the same clock edge on which HLDA is negated. CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] HOLD HLDA BRDY# Figure 66. Basic HOLD/HLDA Operation Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Bus Cycles 169 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet HOLD-Initiated Figure 67 on page 171 shows a HOLD-initiated inquire cycle. In Inquire Hit to Shared this example, the processor samples HOLD asserted during the or Exclusive Line burst memory read cycle. The processor completes the current cycle (until the last expected BRDY# is sampled asserted), asserts HLDA and floats its outputs as described in “ ...
Page 193
... CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# HOLD HLDA EADS# INV Figure 67. HOLD-Initiated Inquire Hit to Shared or Exclusive Line Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Burst Memory Read Bus Cycles Inquire 171 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet HOLD-Initiated Figure 68 on page 173 shows the same sequence as Figure 67 on Inquire Hit to page 171, but in Figure 68 the inquire cycle hits a modified line Modified Line and the processor asserts both HIT# and HITM#. In this example, the processor performs a writeback cycle immediately after the inquire cycle ...
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... Burst Memory Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# HOLD HLDA EADS# INV Figure 68. HOLD-Initiated Inquire Hit to Modified Line Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Writeback Cycle Inquire Bus Cycles 173 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet AHOLD-Initiated AHOLD can be asserted by the system to initiate one or more Inquire Miss inquire cycles. To allow the system to drive the address bus during an inquire cycle, the processor floats A[31:3] and AP off the clock edge on which AHOLD is sampled asserted. The data bus and all other control and status signals remain under the control of the processor and are not floated ...
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... CLK A[31:3] BE[7:0]# AP APCHK# ADS# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV Figure 69. AHOLD-Initiated Inquire Miss Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Read Bus Cycles Inquire 175 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet AHOLD-Initiated In Figure 70 on page 177, the processor asserts HIT# and Inquire Hit to Shared negates HITM# off the clock edge after the clock edge on which or Exclusive Line EADS# is sampled asserted, indicating the current inquire cycle hits either a shared or exclusive line. (HIT# is driven in the same state until the next inquire cycle ...
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... Burst Memory Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV Figure 70. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line Chapter 7 AMD-K6™-IIIE+ Embedded Processor Data Sheet Inquire Bus Cycles 177 ...
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... AMD-K6™-IIIE+ Embedded Processor Data Sheet AHOLD-Initiated Figure 71 on page 179 shows an AHOLD-initiated inquire cycle Inquire Hit to that hits a modified line. During the inquire cycle in this Modified Line example, the processor asserts both HIT# and HITM# on the clock edge after the clock edge that it samples EADS# asserted. ...