AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 251

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
10
10.1
Chapter 10
Write Merge Buffer
EWBE# Control
The AMD-K6-IIIE+ processor contains an 8-byte write merge
buffer that allows the processor to conditionally combine data
from multiple noncacheable write cycles into this merge buffer.
The merge buffer operates in conjunction with the Memory
Type Range Registers (MTRRs). Refer to “Memory Type Range
Registers” on page 231 for a description of the MTRRs.
Merging multiple write cycles into a single write cycle reduces
processor bus utilization and processor stalls, thereby
increasing the overall system performance.
The presence of the merge buffer creates the potential to
perform out-of-order write cycles relative to the processor’s
caches. In general, the ordering of write cycles that are driven
externally on the system bus and those that hit the processor’s
cache can be controlled by the EWBE# signal. See “EWBE#
(External Write Buffer Empty)” on page 110 for more
information.
If EWBE# is sampled negated, the processor delays the
commitment of write cycles to cache lines in the modified state
or exclusive state in the processor’s caches. Therefore, the
system logic can enforce strong ordering by negating EWBE#
until the external write cycle is complete, thereby ensuring that
a subsequent write cycle that hits a cache does not complete
ahead of the external write cycle.
However, the addition of the write merge buffer introduces the
potential for out-of-order write cycles to occur between writes
to the merge buffer and writes to the processor’s caches.
Because these writes occur entirely within the processor and
are not sent out to the processor bus, the system logic is not able
to enforce strong ordering with the EWBE# signal.
The EWBE# control (EWBEC) bits in the EFER register provide
a mechanism for enforcing three different levels of write
ordering in the presence of the write merge buffer:
Write Merge Buffer
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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