AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 253

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
10.2
Chapter 10
Memory Type Range Registers
Table 42 summarizes the three settings of the EWBEC field for
the EFER register, along with the effect of write ordering and
performance. For more information on the EFER register, see
“Extended Feature Enable Register (EFER)” on page 47.
Table 42. EWBEC Settings and Performance
The AMD-K6-IIIE+ processor provides two variable-range
Memory Type Range Registers (MTRRs)—MTRR0 and
MTRR1—that each specify a range of memory. Each range can
be defined as one of the following memory types:
(GEWBED)
EFER[3]
Uncacheable (UC) Memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. Memory write
cycles are targeted at the specified memory address and a
write allocation does not occur.
Write-Combining (WC) Memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. The processor
conditionally combines data from multiple noncacheable
write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single
write cycle reduces processor bus utilization and processor
stalls, thereby increasing the overall system performance.
This memory type is applicable for linear video frame
buffers.
1
0
0
(SEWBED)
EFER[2]
Write Merge Buffer
0 or 1
1
0
Write
Ordering
None
All except UC/WC
All
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Performance
Best
Close-to-Best
Slowest
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