AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 257
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AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
Lead Free Status / RoHS Status
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23543A/0—September 2000
10.4
Chapter 10
Examples
Suppose that the range of memory from 16 Mbytes to 32 Mbytes
is uncacheable, and the 8-Mbyte range of memory on top of 1
Gbyte is writ e-com binable . Range 0 is def ined as t he
uncacheable range, and range 1 is defined as the write-
combining range.
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 16 Mbytes (0100_0000h)
yields
000_0000_1000_0000b. Because the uncacheable range size
is 16 Mbytes, the physical mask value 0 field is
111_1111_1000_0000b, according to Table 44 on page 234.
Bit 1 of the UWCCR register (WC0) is set to 0 and bit 0 of the
UWCCR register is set to 1 (UC0).
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 1 Gbyte (4000_0000h)
yields
010_0000_0000_0000b. Because the write-combining range
size is 8 Mbytes, the physical mask value 1 field is
111_1111_1100_0000b, according to Table 44 on page 234.
Bit 33 of the UWCCR register (WC1) is set to 1 and bit 32 of
the UWCCR register is set to 0 (UC1).
a
a
Write Merge Buffer
physical
physical
AMD-K6™-IIIE+ Embedded Processor Data Sheet
base
base
address
address
0
1
field
field
235
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