AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 8
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AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
Lead Free Status / RoHS Status
Not Compliant
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AMD-K6™-IIIE+ Embedded Processor Data Sheet
viii
14
15
16
17
18
19
20
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
13.4
13.5
13.6
14.1
14.2
14.3
14.4
14.5
14.6
15.1
15.2
15.3
15.4
15.5
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
17.1
17.2
17.3
18.1
18.2
19.1
19.2
Clock Control ............................................................................ 277
Electrical Data .......................................................................... 287
Signal Switching Characteristics ............................................ 297
Thermal Design ........................................................................ 315
Pin Designations ....................................................................... 323
Package Specifications ............................................................ 333
Ordering Information .............................................................. 335
Cache Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
L2 Cache and Tag Array Testing . . . . . . . . . . . . . . . . . . . . . 264
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Clock Control States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 298
Clock Switching Characteristics for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Clock Switching Characteristics for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . 300
Output Delay Timings for 100-MHz Bus Operation . . . . . . 300
Input Setup and Hold Timings for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Output Delay Timings for 66-MHz Bus Operation . . . . . . . 304
Input Setup and Hold Timings for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . 308
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 315
Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 319
Layout and Airflow Considerations . . . . . . . . . . . . . . . . . . . 319
Pins Designations for CPGA Package . . . . . . . . . . . . . . . . . 324
Pins Designations for OBGA Package . . . . . . . . . . . . . . . . . 328
321-Pin Staggered CPGA Package Specification . . . . . . . . 333
349-Ball OBGA Package Specification . . . . . . . . . . . . . . . . . 334
Preliminary Information
23543A/0—September 2000
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