AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 14
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AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
Lead Free Status / RoHS Status
Not Compliant
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AMD-K6™-IIIE+ Embedded Processor Data Sheet
xiv
Table 40.
Table 41.
Table 42.
Table 43.
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Table 72.
Valid L1 and L2 Cache States and Effect of Inquire Cycles . 225
L1 and L2 Cache States for Snoops, Flushes, and
Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
EWBEC Settings and Performance . . . . . . . . . . . . . . . . . . . . . 231
WC/UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Valid Masks and Range Sizes for UWCCR Register . . . . . . . 234
Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 243
SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
I/O Trap Doubleword Configuration . . . . . . . . . . . . . . . . . . . . 248
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Boundary Scan Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 257
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 259
Supported TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Tag versus Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 274
Operating Ranges for Low-Power AMD-K6™-IIIE+
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Operating Ranges for Standard-Power AMD-K6™-IIIE+
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
DC Characteristics for the AMD-K6™-IIIE+ Processor . . . . . 289
Power Dissipation for Low-Power AMD-K6™-IIIE+
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Power Dissipation for Standard-Power AMD-K6™-IIIE+
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Supported Frequencies and Voltages for Low-Power
AMD-K6™-IIIE+ Processors Enabled with AMD PowerNow!™
Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
CLK Switching Characteristics for 100-MHz Bus Operation . 298
CLK Switching Characteristics for 66-MHz Bus Operation . . 299
Output Delay Timings for 100-MHz Bus Operation . . . . . . . . 300
Input Setup and Hold Timings for 100-MHz Bus Operation . 302
Output Delay Timings for 66-MHz Bus Operation . . . . . . . . . 304
Input Setup and Hold Timings for 66-MHz Bus Operation . . 306
RESET and Configuration Signals for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
RESET and Configuration Signals for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 310
Test Signal Timing at 25 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Package Thermal Specification for Low-Power
AMD-K6™-IIIE+ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Preliminary Information
23543A/0—September 2000
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