AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 281

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
TAP Instructions
Table 52. Supported TAP Instructions
Notes:
1. Following the execution of the EXTEST instruction, the processor must be reset in order to return to normal, non-test operation.
2. These instruction encodings are undefined on the AMD-K6-IIIE+ processor and default to the BYPASS instruction.
3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open during
Chapter 13
Instruction
EXTEST
SAMPLE / PRELOAD
IDCODE
HIGHZ
BYPASS
BYPASS
an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.
1
2
3
00100b–11110b
Encoding
00000b
00001b
00010b
00011b
11111b
Table 51. Device Identification Register
Bypass Register (BR). The BR is a Test Data Register consisting of
a 1-bit shift register that provides the shortest path between
TDI and TDO. When the processor is not involved in a test
operation, the BR can be selected by an instruction to allow the
transfer of test data through the processor without having to
serially scan the test data through the BSR. This functionality
preserves the state of the BSR and significantly reduces test
time.
The BR register is selected by the BYPASS and HIGHZ
instructions as well as by any instructions not supported by the
AMD-K6-IIIE+ processor.
The processor supports the three instructions required by the
IEEE 1149.1 standard — EXTEST, SAMPLE/PRELOAD, and
BYPASS — as well as two additional optional instructions —
IDCODE and HIGHZ.
Table 52 shows the complete set of TAP instructions supported
by the processor along with the 5-bit Instruction Register
encoding and the register selected by each instruction.
Version Code
LSB—The least significant bit (LSB) of the DIR is always set
to 1, as specified by the IEEE 1149.1 standard.
(Bits 31–28)
Xh
Register
BSR
BSR
DIR
Test and Debug
BR
BR
BR
Part Number
(Bits 27–12)
05D0h
Description
Sample inputs and drive outputs
Sample inputs and outputs, then load the BSR
Read DIR
Float outputs and bidirectional pins
Undefined instruction, execute the BYPASS instruction
Connect TDI to TDO to bypass the BSR
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Manufacturer
00000000001b
(Bits 11–1)
(Bit 0)
LSB
1b
259