AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 34

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Enhanced RISC86
Microarchitecture
AMD-K6™-IIIE+
Processor Block
Diagram
12
®
Th e E n h an ce d R I SC 8 6 mi c ro a rch i t e c t ure d ef i ne s t h e
characteristics of the AMD-K6 family of processors. The
innovative RISC86 microarchitecture approach implements the
x86 instruction set by internally translating x86 instructions
into RISC86 operations. These RISC86 operations were
specially designed to include direct support for the x86
instruction set while observing the RISC performance
principles of fixed length encoding, regularized instruction
fields, and a large register set.
Th e Enh a n c e d R I S C8 6 m ic ro arch i t e c t u re u s e d i n t h e
AMD-K6-IIIE+ processor enables higher processor core
performance and promotes straightforward extensions, such as
those added in the current AMD-K6-IIIE+ processor and those
planned for the future. Instead of directly executing complex
x86 instructions, which have lengths of 1 to 15 bytes, the
AMD-K6-IIIE+ processor executes the simpler and easier
fixed-length RISC86 operations, while maintaining the
instruction coding efficiencies found in x86 programs.
The AMD-K6-IIIE+ processor contains parallel decoders, a
centralized RISC86 operation scheduler, and ten execution
units that support superscalar operation — multiple decode,
execution, and retirement—of x86 instructions. These elements
are packed into an aggressive and highly efficient six-stage
pipeline.
As shown in Figure 1 on page 13, the high-performance,
out-of-order execution engine of the AMD-K6-IIIE+ processor is
mated to a split, level-one, 64-Kbyte, writeback cache with 32
Kbytes of instruction cache and 32 Kbytes of data cache.
Backing up the level-one (L1) cache is a large, unified, level-two
(L2), 256-Kbyte, writeback cache. The L1 instruction cache
feeds the decoders and, in turn, the decoders feed the
scheduler. The ICU issues and retires RISC86 operations
contained in the scheduler. The system bus interface is an
industry-standard 64-bit Super7 and Socket 7 demultiplexed
bus.
The AMD-K6-IIIE+ processor combines the latest in processor
microarchitecture to provide the highest x86 performance for
today’s computational systems. The AMD-K6-IIIE+ processor
offers true sixth-generation performance and x86 binary
software compatibility.
Preliminary Information
Internal Architecture
23543A/0—September 2000
Chapter 2