AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 7
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AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
Lead Free Status / RoHS Status
Not Compliant
- Current page: 7 of 370
- Download datasheet (6Mb)
23543A/0—September 2000
Contents
8
9
10
11
12
13
7.5
7.6
8.1
8.2
8.3
8.4
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
10.1
10.2
10.3
10.4
11.1
11.2
11.3
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
13.1
13.2
13.3
Power-on Configuration and Initialization ............................ 199
Cache Organization .................................................................. 205
Write Merge Buffer ................................................................. 229
Floating-Point and Multimedia Execution Units .................. 237
System Management Mode (SMM) ........................................ 241
Test and Debug ......................................................................... 251
Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 168
Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Signals Sampled During the Falling Transition of
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
RESET Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 200
State of Processor After INIT . . . . . . . . . . . . . . . . . . . . . . . . 203
MESI States in the L1 Data Cache and L2 Cache . . . . . . . . 207
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Cache Disabling and Flushing . . . . . . . . . . . . . . . . . . . . . . . 211
L2 Cache Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Cache-Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Cache-Line Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Cache States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Writethrough and Writeback Coherency States . . . . . . . . . 227
A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . 227
EWBE# Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Memory Type Range Registers . . . . . . . . . . . . . . . . . . . . . . . 231
Memory-Range Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 233
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . 237
Multimedia and 3DNow!™ Execution Units . . . . . . . . . . . . 239
Floating-Point and MMX™/3DNow!™ Instruction
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
SMM Operating Mode and Default Register Values . . . . . 241
SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
I/O Trap Doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . 250
Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Three-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . 253
Preliminary Information
AMD-K6™-IIIE+ Embedded Processor Data Sheet
vii
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