AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 161

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.55
Pin Attribute
Summary
Sampled
Chapter 5
WB/WT# (Writeback or Writethrough)
Input
WB/WT#, together with PWT, specifies the data cache-line state
during cacheable read misses and write hits to shared cache
lines.
WB/WT# is sampled on the clock edge that the first BRDY# or
NA# of a bus cycle is sampled asserted. If the cycle is a burst
read, WB/WT# is ignored during the last three assertions of
BRDY #. WB /W T# is sampled during mem ory re ad and
non-writeback write cycles and is ignored during all other types
of cycles.
If WB/WT# = 0 or PWT = 1 during a cacheable read miss or
write hit to a shared cache line, the accessed line is cached
in the shared state. This is referred to as the writethrough
state because all write cycles to this cache line are driven
externally on the bus.
If WB/WT# = 1 and PWT = 0 during a cacheable read miss or
a write hit to a shared cache line, the accessed line is cached
in the exclusive state. Subsequent write hits to the same line
cause its state to transition from exclusive to modified. This
is referred to as the writeback state because the L1 data
cache and the L2 cache can contain modified cache lines
that are subject to be written back—referred to as a
writeback cycle—as the result of an inquire cycle, an
internal snoop, a flush operation, or the WBINVD
instruction.
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
139