AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 270

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
12.7
248
I/O Trap Restart Slot
Table 48 shows the format of the I/O trap doubleword.
Table 48. I/O Trap Doubleword Configuration
The I/O trap doubleword is related to the I/O trap restart slot
(see “I/O Trap Restart Slot”). If bit 1 of the I/O trap doubleword
is set by the processor, it means that SMI# was asserted during
the execution of an I/O instruction. The SMI handler tests bit 1
to see if there is a valid I/O instruction trapped. If the I/O
instruction is valid, the SMI handler is required to ensure the
I/O trap restart slot is set properly. The I/O trap restart slot
informs the processor whether it should re-execute the I/O
instruction after the RSM or execute the instruction following
the trapped I/O instruction.
Note: If SMI# is sampled asserted during an I/O bus cycle a
The I/O trap restart slot at offset FF00h in the SMM state-save
area specifies whether the trapped I/O instruction should be
re-executed on return from SMM. This slot in the state-save area
is called the I/O instruction restart function. Re-executing a
trapped I/O instruction is useful, for example, if an I/O write
occurs to a disk that is powered down. The system logic
monitoring such an access can assert SMI#. Then the SMM
service routine would query the system logic, detect a failed I/O
write, take action to power-up the I/O device, enable the I/O
trap restart slot feature, and return from SMM.
The fields of the I/O trap restart slot are defined as follows:
I/O Port
Address
31—16
Bits 31–16—Reserved
Bits 15–0—I/O instruction restart on return from SMM:
0000h = execute the next instruction after the trapped
I/O instruction
00FFh = re-execute the trapped I/O instruction
minimum of three clock edges before BRDY# is sampled
asserted, the associated I/O instruction is guaranteed to be
trapped by the SMI handler.
System Management Mode (SMM)
Preliminary Information
Reserved
15—4
REP String
Operation
3
Operation
I/O String
2
Instruction
Valid I/O
23543A/0—September 2000
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Chapter 12
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