AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 41
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AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
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23543A/0—September 2000
Figure 4. AMD-K6™-IIIE+ Processor Decode Logic
Chapter 2
RISC86
On-Chip ROM
®
Sequencer
operation — a register-to-register add. More complex x86
instructions are decoded into several RISC86 operations.
The AMD-K6-IIIE+ processor uses a combination of decoders to
convert x86 instructions into RISC86 operations. The hardware
consists of three sets of decoders—two parallel short decoders,
one long decoder, and one vector decoder.
Parallel Short Decoders. The two parallel short decoders translate
the most commonly-used x86 instructions ( moves, shifts,
branches, ALU, FPU) and the extensions to the x86 instruction
set (including MMX and 3DNow! instructions) into zero, one, or
two RISC86 operations each. The short decoders only operate
on x86 instructions that are up to seven bytes long. In addition,
Instruction Buffer
Vector Address
Internal Architecture
Short Decoder #1
Short Decoder #2
Long Decoder
Vector Decoder
AMD-K6™-IIIE+ Embedded Processor Data Sheet
4 RISC86 Operations
19
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