AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 152

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.43
Pin Attribute
Summary
Sampled
130
SMI# (System Management Interrupt)
Input, Internal Pullup
The assertion of SMI# causes the processor to enter System
Management Mode (SMM). Upon recognizing SMI#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the interrupt by asserting SMIACT# after
4. Saves the internal processor state in SMM memory
5. Disables interrupts by clearing the interrupt flag (IF) in
6. Jumps to the entry point of the SMM service routine at the
See “System Management Mode (SMM)” on page 241 for more
details regarding SMM.
SMI# is sampled and latched as a falling edge-sensitive signal.
SMI# is sampled on every clock edge but is not recognized until
the next instruction boundary. If SMI# is to be recognized on
the instruction boundary associated with a BRDY#, it must be
sampled asserted a minimum of three clock edges before the
BRDY# is sampled asserted.
A second assertion of SMI# while in SMM is latched but is not
recognized until the SMM service routine is exited.
sampling EWBE# asserted (if EWBE# is masked off, then
SMIACT# is not affected by EWBE#)
EFLAGS and disables NMI interrupts
SMM base physical address, which defaults to 0003_8000h
in SMM memory
If SMI# is asserted synchronously (see Table 19 on
page 140), it can be asserted for a minimum of one clock.
If SMI# is asserted asynchronously, it must have been
negated for a minimum of two clocks followed by an
assertion of a minimum of two clocks.
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5