AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 43

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
2.4
Chapter 2
Centralized Scheduler
MMX™ and 3DNow!™ Instructions. All of the MMX and 3DNow!
instructions, with the exception of the EMMS, FEMMS, and
PREFETCH instructions, are hardware decoded as short
decodes. The MMX instruction decode generates a RISC86
MMX operation and, optionally, an associated MMX load or
store operation. A 3DNow! instruction decode generates a
RISC86 3DNow! operation and, optionally, an associated load or
store operation. MMX and 3DNow! instructions can be decoded
in either or both of the short decoders.
The scheduler is the heart of the AMD-K6-IIIE+ processor (see
Figure 5 on page 22). It contains the logic necessary to manage
out-of-order execution, data forwarding, register renaming,
simultaneous issue and retirement of multiple RISC86
operations, and speculative execution.
The scheduler’s buffer can hold up to 24 RISC86 operations.
This equates to a maximum of 12 x86 instructions. The
scheduler can issue RISC86 operations from any of the 24
locations in the buffer. When possible, the scheduler can
simultaneously issue a RISC86 operation to any available
e x e c u t i o n u n i t ( s t o re , l o a d , b ra n ch , re g i s t e r X
integer/multimedia, register Y integer/multimedia, or
floating-point). In total, the scheduler can issue up to six and
retire up to four RISC86 operations per clock.
The main advantage of the scheduler and its operation buffer is
the ability to examine an x86 instruction window equal to 12
x86 instructions at one time. This advantage is due to the fact
that the scheduler operates on the RISC86 operations in
parallel and allows the AMD-K6-IIIE+ processor to perform
dynamic on-the-fly instruction code scheduling for optimized
execution. Although the scheduler can issue RISC86 operations
for out-of-order execution, it always retires x86 instructions in
order.
Internal Architecture
AMD-K6™-IIIE+ Embedded Processor Data Sheet
21