AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 276

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

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AMD-K6™-IIIE+ Embedded Processor Data Sheet
TAP Signals
254
The test signals associated with the TAP controller are as
follows:
Refer to “Electrical Data” on page 287 and “Signal Switching
Charac t er ist ics” o n pa ge 29 7 t o obt a in t he e lec t ric a l
specifications of the test signals.
TCK—The Test Clock for all TAP operations. The rising
edge of TCK is used for sampling TAP signals, and the
falling edge of TCK is used for asserting TAP signals. The
state of the TMS signal sampled on the rising edge of TCK
causes the state transitions of the TAP controller to occur.
TCK can be stopped in the logic 0 or 1 state.
TDI—The Test Data Input represents the input to the most
significant bit of all TAP registers, including the IR and all
test data registers. Test data and instructions are serially
shifted by one bit into their respective registers on the rising
edge of TCK.
TDO—The Test Data Output represents the output of the
least significant bit of all TAP registers, including the IR and
all test data registers. Test data and instructions are serially
shifted by one bit out of their respective registers on the
falling edge of TCK.
TMS—The Test Mode Select input specifies the test
function and sequence of state changes for boundary-scan
testing. If TMS is sampled High for five or more consecutive
clocks, the TAP controller enters its reset state.
TRST#—The Test Reset signal is an asynchronous reset that
unconditionally causes the TAP controller to enter its reset
state.
Preliminary Information
Test and Debug
23543A/0—September 2000
Chapter 13