AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 369
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AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
Lead Free Status / RoHS Status
Not Compliant
- Current page: 369 of 370
- Download datasheet (6Mb)
23543A/0—September 2000
VID[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
VID[4:0] Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
VIDC Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
VIDO Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Voltage
VSS Pins
W
W/R# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
WB/WT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
WBINVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
WC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
WHCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Write
Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Write/Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Writeback . . . . . . . . . 105
Index
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
RESET requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
unused active low inputs . . . . . . . . . . . . . . . . . . . . . . . . . 295
active high signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
active low signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
bus divisor (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
CLK switching characteristics . . . . . . . . . . . . . . . . . . . . . 298
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
dual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
input low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
plane isolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
VCC2 detect signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
VCC2 High/Low Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
VCC2DET signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
voltage identification control (table) . . . . . . . . . . . . . . . 147
connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
pin designations (table) . . . . . . . . . . . . . . . . . . . . . . 327
unused active high inputs . . . . . . . . . . . . . . . . . . . . . . . . 295
allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . 208
handling control register (WHCR) . . . . . . . . . . . . . 202
to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
EWBE# control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
EWBEC settings (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 231
memory type range registers (MTRRs) . . . . . . . . . . . . . 231
memory-range restrictions . . . . . . . . . . . . . . . . . . . . . . . . 233
performance (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
UC/WC Cacheability Control Register (UWCCR). . . . . 232
uncacheable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
write cycle order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
write-combining memory . . . . . . . . . . . . . . . . . . . . . . . . . 231
burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
coherency state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
conditions (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
logic mechanisms and conditions (figure) . . . . . . . . . 219
examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
valid masks and range sizes (table) . . . . . . . . . . . . . . 234
,
107
–
108
,
119
,
126
,
,
–
131
,
165
215
48
,
,
,
–
139
202
216
190
,
,
,
,
,
,
,
,
142
,
–
,
151
293
320
331
219
219
219
220
278
16
,
Write-Combining Memory . . . . . . . . . . . . . . . . . . 49
Writethrough
cycles . . . . . . . . . 94
L1 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
L2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
or writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
coherency state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
. . . . . . . . . . . . . . . . . 178
AMD-K6™-IIIE+ Embedded Processor Data Sheet
,
96
,
–
180
97
,
,
110
182
,
,
113
186
,
,
139
210
,
,
164
264
,
,
172
,
279
230
,
,
176
–
282
231
347
,
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