AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 162

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.56
Table 19. Input Pin Types
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
3. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time
4. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and V
5. During a warm reset, while CLK and V
6. When register bit EFER[3] is set to 1, EWBE# is ignored by the processor.
7. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be sampled on
140
Name
A20M#
AHOLD
BF[2:0]
BOFF#
BRDY#
BRDYC#
CLK
EADS#
EWBE#
FLUSH#
HOLD
times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain
asserted at least two clocks.
of two clocks relative to the negation of RESET.
ification before it is negated.
its negation.
a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which RESET is sampled
negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
3
1
6
2,7
Pin Tables by Type
Type
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock
Synchronous
Synchronous
Asynchronous
Synchronous
CC
are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to
Preliminary Information
Signal Descriptions
Name
IGNNE#
INIT
INTR
INV
KEN#
NA#
NMI
RESET
SMI#
STPCLK#
WB/WT#
2
2
1
2
4,5
1
1
Type
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
23543A/0—September 2000
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