AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 135

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.24
Pin Attribute
Summary
Driven
5.25
Pin Attribute
Summary
Driven
Chapter 5
HIT# (Inquire Cycle Hit)
HITM# (Inquire Cycle Hit To Modified Line)
Output
The processor asserts HIT# during an inquire cycle to indicate
that the cache line is valid within the processor’s L1 and/or L2
caches (also known as a cache hit). The cache line can be in the
modified, exclusive, or shared state.
HIT# is always driven—except in the Three-State Test mode—
which EADS# is sampled asserted. It is driven in the same state
until the next inquire cycle.
Output
The processor asserts HITM # during an inquire cycle to
indicate that the cache line exists in the processor’s L1 data
cache or L2 cache in the modified state. The processor performs
a writeback cycle as a result of this cache hit. If an inquire cycle
hits a cache line that is currently being written back, the
processor asserts HITM # but does not execute another
writeback cycle. The system logic must not expect the processor
to assert ADS# each time HITM# is asserted.
HITM # is always driven — except in the Three-State Test
mode—and, in particular, is driven to represent the result of an
inquire cycle the clock edge after the clock edge on which
EADS# is sampled asserted. If HITM# is negated in response to
the inquire address, it remains negated until the next inquire
cycle. If HITM# is asserted in response to the inquire address, it
remains asserted throughout the writeback cycle and is negated
one clock edge after the last BRDY # of the writeback is
sampled asserted.
and only changes state the clock edge after the clock edge on
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
113